Digital frame synchronizer

Pulse or digital communications – Spread spectrum – Direct sequence

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370102, H04L 700

Patent

active

047649410

ABSTRACT:
A desired positive fractional stuffing ratio is obtained in a frame synchronizer for a digital signal having a channel frame format that included two stuffing bit positions to obtain either positive or negative stuffing. The fractional stuffing ratio is obtained by controllably increasing the duration of a first predetermined number of intervals during which data bits are written into the synchronizer and, then, by controllably decreasing the duration of a second predetermined number of intervals during which data bits are written into the synchronizer. A data bit is forced to be included in one of the stuffing bit positions occurring during each of the first predetermined number of intervals and a non-data bit is forced to be included in one of the stuffing bit positions occurring during each of the second predetermined number of intervals.

REFERENCES:
patent: 3564414 (1971-02-01), Ebert
patent: 4095053 (1978-06-01), Duttweiler et al.
patent: 4347620 (1982-08-01), Black et al.
patent: 4649536 (1987-03-01), Krinock
patent: 4661966 (1987-04-01), Schreiner
"Jitter due to Pulse Stuffing Synchronization", by Chow, IEEE Transactions on Communications, Jul. 1973.
"Jitter Characteristics of Pulse Stuffing Synchronization", by Matsuura et al., pp. 259-264, 1968, IEEE.
"Digital Multiplex Impairments", Transmission Systems for Communications, 5th Ed., Bell Telephone Laboratories, 1982.
J. McEachern et al., "Threshold Modulation for Jitter Reduction", Contribution to T1 Standards Project-T1x1.3, Standards Project: JWC/87-001, SONET Jitter and Wander Liaison, Jan. 30, 1987.
T. Moore, "Jitter Analysis of Asynchronous Payload Mappings", Contribution to T1 Standards Project-T1x1.4, Standards Project: T1x1.4/86-447, Rates and Formats for Fiber Optic Network Interfaces, Nov. 12, 1986.
D. Duttweiler, "Waiting Time Jitter", BSTJ, vol. 51, No. 1, Jan. 1972, pp. 165-207.

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