Digital frame processor pipe line circuit

Details Digital frame processor pipe line circuit Digital frame processor pipe line circuit

1986-11-12

1987-12-01

Boudreau, Leo H.

Image analysis

Histogram processing

For setting a threshold

358137, 358335, 364900, 365220, G06K 900, G06F 1300

Patent

active

047109661

ABSTRACT:
A plurality of digital words representing picture elements are sequentially loaded into a readin register, which words are thereafter written in parallel into a random access memory via a write data register. The words are subsequently readout of the random access memory in parallel into a read data register and to a readout data register which thereafter sequentially transmits the words stored therein to an output circuit. The arrangement is such that each word may flow through the pipeline to be processed during a clock period of P ns; although the RAM response time is greater than P ns.

REFERENCES:
patent: 3967247 (1976-06-01), Andersen et al.
patent: 4302775 (1981-11-01), Widergren et al.
patent: 4430675 (1984-02-01), Fujime
patent: 4473850 (1984-09-01), Foerster et al.

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