Digital fractional phase detector

Details Digital fractional phase detector Digital fractional phase detector

2000-06-30

2002-08-06

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By phase

C327S003000, C327S158000, C327S107000

Reexamination Certificate

active

06429693

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to frequency synthesizers, and more particularly to a fractional phase detector that increases the overall resolution of an integer phase-locked loop such that the quantization error of the integer phase-locked loop is corrected.
2. Description of the Prior Art
Frequency synthesizers using analog circuit techniques are well known in the art. Conventional RF frequency synthesizer architectures are analog-intensive and generally require a low loop bandwidth to reduce the familiar and well-known reference or compare frequency spurs. Low loop bandwidths are acceptable for RF-BiCMOS and RF-SiGe processes with weak digital capabilities.
Modern deep sub-micron CMOS processes and their RF-CMOS derivatives, however, are not very compatible with frequency synthesizer designs using analog circuit techniques. The conventional PLL-based frequency synthesizers generally comprise analog-intensive circuitry that does not work very well in a voltage-headroom-constrained aggressive CMOS environment. Such frequency synthesizers do not take advantage of recently developed high density digital gate technology.
Newer frequency synthesizer architectures have used sigma-delta modulated frequency divider techniques to randomize the above discussed frequency spurs by randomizing the spurious content at the cost of increased noise floor. These techniques have not significantly reduced the undesirable analog content. Other frequency synthesizer architectures have used direct digital synthesis (DDS) techniques that do not work at RF frequencies without a frequency conversion mechanism requiring an analog solution. Further, previous all-digital PLL architectures rely on an over-sampling clock. Such architectures cannot be used at RF frequencies.
In view of the foregoing, it is highly desirable to have a technique to implement a digitally-intensive frequency synthesizer architecture that is compatible with modern CMOS technology and that has a phase quantization resolution of better than +/−&pgr; to accommodate wireless applications.
SUMMARY OF THE INVENTION
The present invention is directed to a digital fractional phase detector for an all-digital phase domain PLL frequency synthesizer that is compatible with deep sub-micron CMOS processes. The all-digital phase domain PLL frequency synthesizer accommodates direct frequency/phase modulation transmission to remove the requirement for an additional transmitting modulator normally associated with wireless digital transmitters. This is accomplished by operating the PLL entirely in the phase domain with maximum digital processing content such that the loop can be of high-bandwidth of “type 1” without the need for a loop filter. A “type 1” PLL loop, as used herein, means a loop having only one integrating pole in the feedback loop. Only one integrating pole exists due to the VCO frequency-to-phase conversion. It is possible therefore, to eliminate a low-pass filter between the phase detector and the oscillator tuning input, resulting in a high bandwidth and fast response of the PLL loop.
According to one embodiment, the all-digital phase domain PLL frequency synthesizer contains only one major analog component, a digitally-controlled 2.4 GHz voltage controlled oscillator (VCO or dVCO). The PLL loop is an all-digital phase domain architecture whose purpose is to generate the 2.4 GHz high frequency f
osc
for the “BLUETOOTH” standard. The underlying frequency stability of the system is derived from a reference crystal oscillator, such as a 13 MHz TCXO for the global system for mobile communications (GSM) system. The phase of the VCO output is obtained by accumulating the number of significant (rising or falling) edge clock transitions. The phase of the reference oscillator is obtained by accumulating a frequency control word on every significant (rising or falling) edge of the reference oscillator output that is re-clocked via the VCO output. As used herein, “significant edge” means either a “rising” or a “falling” edge. A ceiling element continuously adjusts a reference phase value associated with the accumulated frequency control word by rounding off to the next integer (alternatively, truncating fractional bits necessary) to compensate for fractional-period delays caused by re-clocking of the reference oscillator by the VCO output. The phase error signal is then easily obtained by using a simple arithmetic subtraction of the VCO phase from the adjusted reference phase on every significant edge of the re-clocked reference oscillator output. The phase error signal can then be used as the tuning input to the digitally-controlled VCO directly via a gain element associated with the PLL loop operation.
Due to the VCO edge counting nature of the PLL (all-digital phase domain architecture), the phase quantization resolution cannot be better than +/−&pgr; radians of the frequency synthesizer VCO clock. The present digital fractional phase detector is capable of accommodating a quantization scheme to measure fractional delay differences between the significant edge of the frequency synthesizer VCO clock and an external reference oscillator clock. According to one embodiment, the digital fractional phase detector has a time-to-digital converter having a resolution determined by an inverter delay associated with a given CMOS process. The digital fractional phase is determined by passing the frequency synthesizer VCO clock through a chain of inverters such that each inverter output will produce a clock pulse slightly delayed from that of the immediately previous inverter. The resultant staggered clock phases would then be sampled by the same reference clock.
In one aspect of the invention, a digital fractional phase detector system is provided that allows fast design turn-around using automated CAD tools.
In still another aspect of the invention, a digital fractional phase detector system is provided to implement an all-digital phase domain PLL frequency synthesizer having much less undesirable parameter variability than normally associated with analog circuits.
In yet another aspect of the invention, a digital fractional phase detector system is provided to implement an all-digital phase domain PLL frequency synthesizer having enhanced testability features.
In yet another aspect of the invention, a digital fractional phase detector system is provided to implement an all-digital phase domain PLL frequency synthesizer that requires desirably low silicon area to physically implement.
In yet another aspect of the invention, a digital fractional phase detector system is provided to implement an all-digital phase domain PLL frequency synthesizer that requires lower power than conventional frequency synthesizers.
In still another aspect of the invention, a digital fractional phase detection system is provided to implement an all-digital phase domain PLL frequency synthesizer having direct frequency/phase modulation transmission capability to minimize system transmitter requirements.
In still another aspect of the invention, a digital fractional phase detection system is provided to implement an all-digital phase domain PLL frequency synthesizer that accommodates the “BLUETOOTH” communication protocol.
In yet another aspect of the invention, a digital fractional phase detection system is provided to increase the overall resolution of an integer phase-locked loop such that the quantization error of the integer phase-locked loop is corrected.


REFERENCES:
patent: 5568071 (1996-10-01), Hoshino et al.
patent: 5796682 (1998-08-01), Swapp
patent: 6125158 (2000-09-01), Carson et al.

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