Digital fractional-N phase lock loop and method thereof

Details Digital fractional-N phase lock loop and method thereof Digital fractional-N phase lock loop and method thereof

2011-08-16

2011-08-16

Kinkead, Arnold (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Tuning compensation

C331S00100A, C331S025000, C331S17700V, C327S156000, C327S159000

Reexamination Certificate

active

07999623

ABSTRACT:
A method for reducing a phase noise in a digital fractional-N phase lock loop (PLL) is disclosed. The method comprises: quantifying a time difference between a reference clock and a feedback clock into a time difference signal; generating a residual error signal according to the time difference signal and an instantaneous error signal; filtering the residual error signal to generate a control code; controlling an oscillator using the control code to generate an output clock; receiving a fractional number between 0 and 1 to generate the instantaneous error signal; and dividing down the output clock by a divisor value according to the fractional number.

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patent: 6960947 (2005-11-01), Albasini
patent: 7183860 (2007-02-01), Staszewski
patent: 7205924 (2007-04-01), Vemulapalli
patent: 429688 (2001-04-01), None
patent: 587371 (2004-05-01), None
patent: I226754 (2005-01-01), None

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