Digital FM demodulator with reduced quantization noise

Details Digital FM demodulator with reduced quantization noise Digital FM demodulator with reduced quantization noise

1999-06-07

2004-11-16

Ghayour, Mohammad H. (Department: 2631)

Pulse or digital communications

Receivers

Angle modulation

C375S316000, C375S285000, C375S371000

Reexamination Certificate

active

06819723

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to digital frequency-modulation (FM) demodulation and more particularly, to a digital FM demodulator that extracts a digital time sequence from an intermediate frequency (IF) carrier while reducing quantization error and eliminating a requirement of a reference clock.
2. Description of the Prior Art
Frequency modulation (FM) is an important and common method of information conveyance in radio communication systems. The receiver end of the system contains the FM demodulation circuit which is often of analog including a detector circuit and a phase lock loop (PLL) circuit. Often, the necessary circuitry to implement an FM demodulator is constructed on an integrated circuit chip. If the detector is brought into the integrated circuit, then a larger chip area is required. If the PLL is built into the integrated circuit, then an external capacitor is necessary outside the chip.
If the modulated signal requires digital signal processing after demodulation, then the circuit described above requires an analog-to-digital converter to convert the demodulated analog signal into digital signal. The analog signal is easily interfered with by noise. To reduce noise, the digital FM demodulator will first convert the modulated intermediate-frequency (IF) signal into a digital signal by way of an analog-to-digital converter, thereafter using a digital signal processor to demodulate the modulation signal. The analog-to-digital converter and digital signal processor used in the conventional digital FM demodulator must operate at high speed to demodulate the modulation signal in real time. The system could use a reference clock with a multiple-fold frequency of modulation signal for sampling the input signal to detect its phase change and then demodulate the signal, but such technology requires a high frequency reference clock.
The conventional methods of digital RF communication always need to convert the analog signal into digital signal in the receiver end with the drawbacks of increasing the circuit complexity. Thus, a demodulation circuit combining the detector circuit of a PLL with a carefully chosen analog-to-digital circuit to reduce quantization error could result in accurate demodulation while simplifying circuit design.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a new digital FM demodulator applicable to radio communication systems such as pagers, cellular phones, Global Positioning Satellite (GPS) systems, and Digital Enhanced Cordless Telecommunication (DECT) systems.
The next object of the present invention is to provide a digital FM demodulator implemented with an analog-to-digital converter. The input intermediate-frequency signal passes through the inventive demodulator thereby generating a digital signal including a high-frequency quantization noise signal. Then, by way of a low-pass filter, the quantized noise signal is filtered to acquire the baseband signal.
A further objective of the present invention is to provide a digital FM demodulator which adapts a PLL structure and utilizes the concept of delta-sigma analog-to-digital conversion which does not require external components or a high frequency reference clock.
The present invention provides advantages over similar systems in the prior art by using delay lines as the timing reference and by adapting the concept of delta-sigma analog-to-digital conversion to achieve the time-to-digital conversion of digital FM demodulation. This digital FM demodulator includes delay lines, an m-to-1 multiplexer, a phase detector, a charge pump circuit, a quantizer and a digital integrator. The modulation signal on an intermediate frequency carrier passes through the delay lines, each having a delay time of around one cycle time, and the phase of the delayed signal is compared with the phase of the original signal. This comparison produces a pulse which is applied to the charge pump circuit where a cumulative charge is stored in a capacitor. This charge is quantized into a voltage level which is accumulated by the digital integrator. Then, a new sample of another output signal of the delay lines is taken and compared in phase with the input signal. This system is similar to a PLL, i.e., it is a feedback system taking phase as the error signal. The quantized digital signal will feed through the low-pass filter defined by the sampling rate if the system to filter out high frequency noise and get the original modulation signal, i.e., the modulation signal is the digital output signal.


REFERENCES:
patent: 5465396 (1995-11-01), Hunsinger et al.
patent: 5698786 (1997-12-01), Andersen
patent: 5700952 (1997-12-01), Andersen
patent: 5804729 (1998-09-01), Andersen
patent: 5831167 (1998-11-01), Andersen

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