Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1999-01-26
2001-08-21
Mai, Tan V. (Department: 2121)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S320000, C708S316000
Reexamination Certificate
active
06279021
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to digital filters that are used for digital audio devices in order to execute digital data separation and/or synthesis.
2. Description of the Related Art
A Finite Impulse Response (FIR) type digital filter is constructed so that output data Y(n) will be produced by convoluting input data X(n) and impulse responses, as expressed by equation (1).
Y
(
n
)
=
∑
k
=
0
N
-
1
h
(
k
)
·
X
(
n
-
k
)
(
1
)
where, h(k) is a filter coefficient and N is the number of taps. When transformed with regard to Z, the equation (1) will be as follows:
H
(
z
)
=
∑
n
=
0
N
-
1
h
(
n
)
·
Z
-
n
(
2
)
The equation (2) will be further transformed as follows:
H
(
ⅇ
j
ω
)
=
∑
n
=
0
N
-
1
h
(
n
)
·
ⅇ
-
j
ω
n
(
3
)
The equation (3) determines a frequency response. Assuming that &ohgr;=2&pgr;k/N, the equation (3) will be as follows:
H
(
ⅇ
j
ω
)
-
∑
n
=
0
N
-
1
h
(
n
)
·
ⅇ
-
j
2
π
n
k
/
N
(
4
)
This equation (4) may be regarded as an expression of Discrete Fourier Transformation (DFT). Thus, the filter coefficient h(k) is obtained through Inverse Discrete Fourier Transformation (IDFT) of the frequency characteristic given by the equation 4.
FIG. 1
shows the circuit of a standard FIR type digital filter.
In this filter circuit, a plurality of delay elements
1
, which may be, for example, shift registers, are connected in series with each other and each of these elements delays the input data X(n) a certain period T. This circuit also has a plurality of multipliers
2
, the first multiplier connected to the input data X(n) carrying line to the first delay element
1
and the remaining connected to the output line from each delay element
1
. The first multiplier
2
multiplies the input data X(n) by a given filter coefficient h(k) and the remaining multipliers
2
multiply the output from each delay element
1
by the same filter coefficient h(k). In this way, the input data X(n) is convoluted with the impulse responses.
A total sum adder
3
, included in this circuit, sums up the outputs from all the multipliers
2
, that is, the input data X(n) and the outputs from all delay elements
1
after being multiplied by the predetermined filter coefficient h(k), and produces output data Y(n). Consequently, the input data X(n) has now been processed, subject to the arithmetic operation in compliance with the above-mentioned equation (1).
Because an array of delay elements
1
and multipliers
2
, corresponding to the number of taps N are required, this type of digital filter has a problem that its entire circuit size becomes larger as the number of the taps increases. Therefore, a digital filter using a stored program method has been proposed which stores time-series input data in a memory once and sequentially multiplies the input data by the filter coefficient after reading it from the memory, while accumulating the product of each multiplication.
FIG. 2
shows a block diagram representing the digital filter using the stored program method.
In this block diagram, a RAM
11
sequentially stores time-series input data X(n) that has been input to it from moment to moment. A plurality of filter coefficients h(k) are stored in a ROM
12
. Input data X(n) stored in the RAM
11
is read out at its arithmetic step and from the ROM
12
a step-specific filter coefficient h(k) with a value of k incrementing step by step is read out, where k corresponds to the k described in equation (1). Then, a multiplier
13
multiplies the input data X(n−k) read from the RAM
11
by the filter coefficient h(k) read from the ROM
12
.
An accumulator
14
, consisting of an adder
15
and a register
16
, accumulates the product of each multiplication executed by the multiplier
13
. Specifically, the adder
15
adds the output from the multiplier
13
and the output from the register
16
and the resultant sum is stored into the register
16
again. In this way, the product of each multiplication executed by the multiplier
13
is heated up sequentially. An output register
17
receives an accumulation value output from the accumulator
14
and outputs it as output data Y(n).
After reading the input data X(n) and the filter coefficient h(k) sequentially from the RAM
11
and ROM
12
, respectively, the FIR type digital filter repeats the product sum arithmetic operation and produces the output data Y(n), thus processing the arithmetic of equation (1). This type of a digital filter does not become large, even if the filter circuit includes a large number of taps N.
One digital filter is assumed to have the first filter coefficient h
1
(n), whereas another digital filter is assumed to have the second filter coefficient h
2
(n) given by the following equation:
h
2
(
n
)=(−1)
n
−h
1
(
n
) (5)
The latter digital filter is referred to as a mirror filter because of its frequency response characteristics. The arithmetic relation of this filter with Z transformation can be expressed as follows:
H
2
(
z
)
=
∑
n
=
-
∞
∞
Z
-
n
·
h
2
(
n
)
=
∑
n
=
-
∞
∞
Z
-
n
·
(
-
1
)
-
n
·
h
1
(
n
)
=
H
1
(
-
Z
)
(
6
)
When we consider the frequency response characteristics of the filter, the following equation is obtained:
h
2
(
n
)=
e
j&pgr;n
·h
1
(
n
) (7)
When equation (7) is assigned to equation (6), the following equation is derived:
H
2
(
e
j&ohgr;
)=
H
1
(
e
j&ohgr;+j&pgr;
) (8)
From equation (8), the frequency response characteristics of the mirror filter are symmetric with regard to &pgr;/2. Because &pgr;/2 is ¼ of the sampling period, the mirror filter is called a Quadrature Mirror Filter (QMF). A QMF of this kind is detailed in a publication “IEEE Transactions on Acoustics Speech and Signal Processing” (Vol. ASSP-32, No. 3, Jun., 1984, pp. 522-531).
A separation filter in which the above-mentioned QMF separates the input data into frequency components in different bands is constructed to produce two output data Ya(n) and Yb(n) which have been separated from the input data X(n). This filter convolutes the input data X(n) with the impulse responses and executes adding and subtracting calculations on the data obtained from the convolution process, as expressed by equations (9) and (10).
Y
a
(
n
)
=
∑
k
=
N
-
1
0
h
(
2
k
)
·
X
(
2
n
-
2
k
)
-
∑
k
=
N
-
1
0
h
(
2
k
+
1
)
·
X
(
2
n
-
2
k
+
1
)
(
9
)
Y
b
(
n
)
=
∑
k
=
N
-
1
0
h
(
2
k
)
·
X
(
2
n
-
2
k
)
+
∑
k
=
N
-
1
0
h
(
2
k
+
1
)
·
X
(
2
n
-
2
k
+
1
)
(
10
)
FIG. 3
shows a block diagram representing the structure of the separation filter in which data separation into different frequency bands is performed according to equations (9) and (10).
As shown in this block diagram, a plurality of delay elements
21
are serially connected and each of these elements delays the input data X(n) a certain period T. Of a plurality of first multipliers
22
, one is connected to the input data X(n) carrying line to the first delay element
21
and the remaining multipliers
22
are connected to the output line from each of the delay elements
21
located in the even number stages. The first multipliers
22
multiply the input data X(n) and the outputs from these delay elements
21
by a filter coefficient h(2k). There are also a plurality of second multipliers
23
connected to the output line from each of the delay elements
21
located in the odd number stages. The second multiplie
Nagao Fumiaki
Takano Koji
Cantor & Colburn LLP
Mai Tan V.
Sanyo Electric Co,. Ltd.
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