Digital filtering circuit

Details Digital filtering circuit Digital filtering circuit

2002-01-17

2004-01-06

Mai, Tan (Department: 2121)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S316000

Reexamination Certificate

active

06675183

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a digital filtering circuit for filtering digital data and more specifically to a digital filtering circuit suitable for filtering an inputted digital video signal in which a luminance signal and color-difference signals are multiplexed in unit of byte (8 bits). The invention also relates to a digital filtering circuit for processing the digital video signal suitably formed in a semiconductor integrated circuit device.
2. Description of the Related Art
A coding format called ITU-R (International Telecommunication Union—Radio communication) Recommendation BT.
601
(hereinafter referred to as BT.
601
) is used often in general as an input format of a digital video signal. Recommendation BT.
601
will be explained below.
Utilizing the fact that the human is not so sensitive to colors, Recommendation BT.
601
reduces color information to a half in the horizontal direction. Sampling frequency of a luminance signal Y is set at 13.5 MHz and sampling frequency of two color-difference signals Cb and Cr is set at 6.75 MHz, i.e., a half of the former. Accordingly, the ratio of the sampling frequencies of the luminance signal Y, the color-difference signal Cb and the color-difference signal Cr is 4:2:2. From this point, this format is called a 4:2:2 coding system or a 4:2:2 digital component signal. Here, the luminance signal Y, the color-difference signal Cb and the color-difference signal Cr are digital data of 8 bits, respectively, per one pixel. That is, the quantizing accuracy is 8 bits. It is noted that when primary color signals are R (red), G (green) and B (blue), the color-difference signal Cb is a digital signal of a difference (B−Y) and the color-difference signal Cr is a digital signal of a difference (R−Y). Although a 4:4:4 coding system and a system in which quantizing accuracy of each of the signals Y, Cb and Cr is set at 10 bits are also stipulated in the format of BT.
601
, the
8
b
it 4:2:2 system which is widely used in general will be explained below.
FIG. 7
shows an outline of the format of Recommendation BT.
601
. In BT.
601
, data are lined in order of pixel 0, 1, 2, . . . from the left of the screen until
719
. Among them, data of the color-difference signals Cb and Cr exist for the pixels affixed with even numbers (0, 2, 4, . . . 718). When the luminance signal Y and the color-difference signals Cb and Cr of a pixel n are represented by Yn, Cbn and Crn, respectively, the data turns out to be a data string in which the luminance signal Y is inserted (interleaved) every other data (per two periods) and the color-difference signals Cb and Cr are inserted every three data (per four periods) regularly in the horizontal direction like Cb
0
, Y
0
, Cr
0
, Y
1
, Cb
2
, Y
2
, Cr
2
, Y
3
, . . . In other words, the luminance signal Y and the color-difference signals Cb and Cr may be considered to be multiplexed. The data is transmitted in synchronism with a transmission clock of 27 MHz in line in the horizontal direction in order from the smaller line number (in order of pixel 0, 1, 2, . . . ). Accordingly, the data string or the data stream of Recommendation BT.
601
is a data string or a data stream in which the luminance signals Y, color-difference signals Cb and Cr are interleaved respectively in unit of 8 bits and which is synchronized with the clock of 27 MHz.
It is noted that there is a case when a filtering process is implemented to the digital video signal inputted in the format of the above-mentioned Recommendation BT.
601
for the purpose of removing noises and of restricting a band in systems handling the digital video signal such as a digital broadcasting receiver, a digital camera and a video phone.
A case of implementing a filtration operation on the data string of Recommendation BT.
601
by a known transversal filter in the horizontal direction will be explained below.
It is noted that although the transversal filter itself is known, the structure of a digital filtering circuit shown in
FIGS. 2 and 4
, i.e., a combination circuit of the transversal filter and a timing operation explained in
FIGS. 3 and 5
are not publicly known and are a digital filtering circuit and its timing operation discussed by the inventors in the process of devising the present invention.
In implementing the filtration operation by the transversal filter, it is conceivable of implementing the filtering process in the independent digital filtering circuits respectively after separating the luminance signal Y and the two color-difference signals Cb and Cr from the data string in which the luminance signals and the color-difference signals are multiplexed.
FIG. 2
shows the structure of the digital filtering circuit in performing filtration operations of three taps. In the digital filtering circuit in
FIG. 2
, filtration operating sections of the luminance signal Y and the color-difference signals Cb and Cr are formed independently from each other. Each of the filtration operating sections
201
,
202
and
203
which are set as the transversal filter comprises a delay line composed of three D flip-flops
10
, three multipliers
30
,
31
and
32
for multiplying the three taps of the delay line by adequate tap coefficients a
0
, a
1
and a
2
and an adder
40
for adding and outputting the result of the three multipliers. It is noted that each D flip-flop
10
is a D flip-flop of 8 bits and latches input data at the rising edge of clocks clk
2
, clk
3
and clk
4
to be supplied.
The D flip-flop
10
at the input stage of each of the filtration operating sections
201
,
202
and
203
separates data from an input node IN by receiving clocks clk
2
, clk
3
and clk
4
which are generated by a clock generator circuit
60
described later and which are different from each other.
FIG. 3
is a timing chart of the clock input and output data d
0
, d
1
and d
2
of the D flip-flop
10
on each input stage. The clock clk
2
of 13.5 MHz is used for the luminance signal Y and the clocks clk
3
and clk
4
of 6.75 MHz are used for the color-difference signals Cb and Cr, respectively, as the clock inputted to the input stage D flip-flop
10
. These clocks clk
2
, clk
3
and clk
4
are generated by the clock generator circuit
60
based on a clock clk
1
of 27 MHz which is synchronism with the data string of BT.
601
inputted from the input node IN. As shown in the time chart in
FIG. 3
, the data string inputted from the input node IN may be separated into data strings of the luminance signal Y, the color-difference signal Cb and the color-difference signal Cr like the output data d
0
, d
1
and d
2
, respectively, and the filtering operation may be implemented independently by latching at the rising edge of the clocks clk
2
, clk
3
and clk
4
.
Next, a digital filtering circuit in filtering in two directions of the horizontal and vertical directions will be explained.
FIG. 4
shows the structure of the digital filtering circuit in implementing the filtering process of three taps both in the horizontal and vertical directions as an example. This digital filtering circuit will be explained below.
The digital filtering circuit in
FIG. 4
is what a filtration operating section comprising a horizontal direction filtering section and a vertical direction filtering section is structured for the luminance signal Y, the color-difference signal Cb and the color-difference signal Cr independently from each other. The configuration of the horizontal direction filtering section HF is equal to that of the digital filtering circuit in FIG.
2
. The vertical direction filtering section VF comprises a delay line composed of two line memories, three multipliers
33
,
34
and
35
for multiplying three taps of the delay line by tap coefficients, respectively, and an adder
41
for adding outputs of the three multipliers in each filtration operating section.
Each line memory is a FIFO (First In First Out) memory and has a data capacity of one line of data string to be processed in each of the filtrati

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