Digital filter tune loop

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Unwanted signal suppression

Reexamination Certificate

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Details

C327S552000

Reexamination Certificate

active

06356142

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to communications systems and, more specifically, to tunable filters used in communications systems.
2. Description of the Prior Art
Many communications devices include filters to filter out noise and that modulate and demodulate signals. These filters typically consist of capacitors and resistors and have a predictable frequency response based on the capacitance of the capacitors and the resistance of the resistors used. The predictability of the frequency response is tied to the precision of the capacitors and the resistors. If, for example, a filter includes capacitors and resistors that have precisely known capacitance and resistance, respectively and that are immune to variations in operating temperature, then the frequency characteristic of the resulting filter would also be known, irrespective of the environment in which it was used.
Unfortunately, many capacitors and resistors have parameter values that deviate from their rated parameter values within a known range. Also, the parameter values of such elements tend to vary widely with certain environmental factors, such as temperature. Therefore, to achieve the precision required for certain communications systems, the filters in a system are calibrated prior to use. Typically, a filter in a communications system will include a array of switchable elements. For example, a filter could include an array of capacitors, each of which is coupled to the filter through a controllable switch. Thus, if a given switch is closed, a corresponding capacitor is coupled to the filter and if the switch is open, the capacitor is isolated from the total filter capacitance.
The communications system will undergo a calibration process in which a tuning signal generator sends a tuning signal, having a frequency equal to the target frequency of the filter, to drive the filter and a delay circuit in parallel with the filter. The tuning signal could be at a frequency other than the target frequency of the filter. In such a case, the delay of the reference path would be other than 45 degrees for a first order filter. The delay circuit delays the tuning signal by an amount of time corresponding to the delay expected from the filter for a signal having a frequency equal to the target frequency. The difference in the delay through the filter and through the delay circuit is determined by comparing the leading edge of the tuning signal from the filter to the leading edge of the tuning signal from the delay circuit. A counter, triggered by a clock circuit, counts the time between the leading edges and activates a number of switchable elements corresponding to the number of counts of the counter. Because the counter lacks resolution superior to that of the clocking circuit, the precision of the filter tuning process for a first order filter is limited by the resolution of the clocking circuit. Unfortunately, many existing clocking circuits have clocking speeds limited by the available system clock.
Therefore, there is a need for a switchable element array-type filter tuning circuit that has a precision greater than the precision of the clocking circuit used by the tuning circuit.


REFERENCES:
patent: 5245646 (1993-09-01), Jackson et al.
patent: 5745001 (1998-04-01), Ueshima et al.
patent: 5914633 (1999-06-01), Comino et al.
Roland E. Best, “Phase-Locked Loops” McGraw-Hill, 1999, pp. 177-210.

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