Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2007-05-29
2007-05-29
Ngo, Chuong D. (Department: 2193)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
10260627
ABSTRACT:
A digital filter realization is proposed that consists of only one multiplier, i. e. which operates with a higher clock rate and changes coefficient at the multiplier each clock cycle, but in which the clock rate of the multiplier is reduced in comparison to prior art filters by considering equal filter coefficients, e. g. based on the symmetry of FIR filter coefficients. According to the present invention preferably the samples belonging to equal filter coefficients are added in advance in order to reduce the number of multiplications, which concludes in a reduced clock rate for the filter, a reduced needed calculation power, and therefore a reduced power consumption.
REFERENCES:
patent: 3930147 (1975-12-01), Bellanger et al.
patent: 4779128 (1988-10-01), Johannes et al.
patent: 5040137 (1991-08-01), Sherrill
patent: 5079734 (1992-01-01), Riley
patent: 5594675 (1997-01-01), Peng
patent: 5777912 (1998-07-01), Leung et al.
patent: 6505221 (2003-01-01), Maschmann
patent: 31 11 889 (1982-10-01), None
patent: 0 774 835 (1997-05-01), None
patent: 0 977 359 (2000-02-01), None
Nöthlings Rolf
Wildhagen Jens
Ngo Chuong D.
Sony Deutschland GmbH
LandOfFree
Digital filter realization does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Digital filter realization, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital filter realization will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3729541