Digital filter for reducing voltage peaks

Details Digital filter for reducing voltage peaks Digital filter for reducing voltage peaks

2006-10-24

2006-10-24

Corrielus, Jean B. (Department: 2611)

Pulse or digital communications

Receivers

Interference or noise reduction

C375S346000, C455S307000, C708S300000

Reexamination Certificate

active

07127015

ABSTRACT:
The present invention relates to a digital filter suitable for receiving a digital input signal (INPUT(G)) comprising a voltage peak also known as glitch (G). It is characterized in that it comprises:a delay line (T) adapted to produce a delayed digital input signal (INPUT(G)+Δt),rising edge (PD) and falling edge (ND) detectors adapted to produce rising (P) and falling (N) edge indicator signals respectively from the delayed digital input signal (INPUT(G)+Δt),first (M1) and second (M2) mixing means adapted to produce rising (P′) and falling (N′) edge filter indicator signals respectively from said digital input signal (INPUT(G)) and said rising (P) and falling (N) edge indicator signals respectively,third mixing means (M3) adapted to produce a digital output signal (OUTPUT) without a glitch from the rising edge filter indicator signal (P′) and from the falling edge filter indicator signal (N′).

REFERENCES:
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patent: 6628999 (2003-09-01), Klaas et al.
patent: 6700943 (2004-03-01), Miller
patent: 6937084 (2005-08-01), Bowling

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