Digital filter for filtering and decimating delta sigma modulato

Details Digital filter for filtering and decimating delta sigma modulato Digital filter for filtering and decimating delta sigma modulato

1992-03-02

1993-01-19

Logan, Sharon D.

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

3647241, 36472404, H03M 302, G06F 1531

Patent

active

051810336

ABSTRACT:
An oversampled interpolative delta sigma analog-to-digital converter including a delta sigma modulator is provided with a cascade of bit-slice elements at the output of the modulator to form a filter/decimator. Each bit-slice element includes a filter circuit that filters the bit-rate signal in accordance with an arbitrary filter impulse response input signal to provide the converter with a filter characteristic that can be controllably varied without modifying the filter hardware. In each bit-slice element, an adder circuit and a delay circuit decimate the bit-rate signal produced by the delta sigma modulator to provide a digital output signal at a clock cycle rate equal to the Nyquist rate. The filter/decimator also provides encoding of the delta sigma output in 2's complement format.

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J. C. Candy, "A Use of Limit Cycle Oscillators to Obtain Robust Analog to Digital Converters", IEEE Transactions on Communications, vol. COM-22, No. 3, Mar. 1974, pp. 298-305.
J. C. Candy et al., "Using Triangularly Weighted Interpolation to get 13-Bit PCM from a Sigma-Delta Modulator", IEEE Transactions on Communications, vol. COM-24, No. 11, Nov. 1976, pp. 1268-1275.
A. V. Oppenheim et al., "Digital Signal Processing", Prentice-Hall International Inc. (1975) pp. 155-165.

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