Digital filter employing parallel processing

Details Digital filter employing parallel processing Digital filter employing parallel processing

1988-04-29

1990-08-07

Harkcom, Gary V.

Boots, shoes, and leggings

G06F 1531

Patent

active

049473620

ABSTRACT:
An adaptive digital filter can be implemented on a single Very Large Scale Integrated (VLSI) circuit silicon chip and the Least Mean Square adaptive filter algorithm can be performed by parallel processing during a single clock cycle. The adaptive filter contains dual delay lines to yield a sequence of simultaneous samples of both input and output signals. Correlations of the present error difference with previous samples of both input and output signals can then take place simultaneously in each clock cycle. The adaptive filter is modular and can be cascaded with other identical filters to form a high-order filter.

REFERENCES:
patent: 3665171 (1972-05-01), Morrow
patent: 4038536 (1977-07-01), Feintuch
patent: 4754419 (1988-06-01), Iwata
B. Widrow et al., "Adaptive Signal Processing", Prentice-Hall, Inc. Englewood Cliffs, N.J. 07632, 1985, pp. 98-116.
B. Ahuja et al., "A Sampled Analog MOS LSI Adaptive Filter", IEEE Trans. on Communications, vol. COM-27, No. 2, Feb. 1979, pp. 406-412.

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