Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1998-12-16
2001-02-20
Mai, Tan V. (Department: 2121)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S316000, C708S319000
Reexamination Certificate
active
06192386
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a digital filter, digital signal processing method, and communication apparatus.
2. Description of the Related Art
In a case where m bit data are made into m x bit data by an x-time interpolation circuit, and a digital signal process is carried out with the m*x bit data inputted into a digital filter, the number of delay elements (stages of a shift register) which constitutes a digital filter is increased in proportion to the interpolation ration x. Furthermore, the operating frequency of the digital filter is multiplied x times. Accordingly, the consumption power of the digital filter is increased, and if the digital filter is placed on integrated circuits, the area of occupation thereof is also increased.
Furthermore, in a case where serial data of a plurality of series are digitally signal-processed in parallel to each other in each of the series, it is necessary to prepare a plurality of digital filters, thereby resulting in a further increase in the consumption power and in the area of occupation on the integrated circuit chips.
SUMMARY OF THE INVENTION
Therefore, it is one of the objects of the invention to provide a compact digital filter which has a feature of processing by interpolating digital signals x times (wherein x is a natural figure of 4 or more) and the consumption of which is suppressed to be low.
A digital filter according to the invention includes a plurality of stages of delay elements into which serial data are inputted, and a plurality of data distributors which distribute the respective output data of the plurality of stages of delay elements into x different signal channels by a time-sharing system, wherein the respective data distributors operate x times the input rate of the serial data.
Since the data distributors distribute data at a high rate, the number of data processed by the digital filter becomes x times, and the data are interpolated. On the other hand, the number of delay elements becomes one-xth times the conventional number, and the operating frequency of a plurality of stages of delay elements also becomes one-xth times.
One of the preferred modes of a digital filter according to the invention includes a multiplier which multiplies the output data of the respective data distributors by the coefficient of the digital filter, and x groups of adders.
Furthermore, another preferred mode of the digital filter according to the invention is made into a zero inserted type interpolation filter.
Furthermore, still another preferred mode of the digital filter according to the invention prepares only the multiplying coefficients equivalent to half at one side in digital filter coefficients, utilizing the symmetry of even-ordered and even-symmetrical digital filter coefficients, inputs the respective output data of a pair of delay elements in the symmetrical position into one of the data distributors, and distributes the respective data by a time-sharing system. Thereby, it is possible to further decrease the number of digital filter coefficients, multipliers, and adders by one half.
Furthermore, another preferred mode of the digital filter according to the invention reverses the direction of distributement of the respective data when distributing the respective output data of a pair of delay elements in the symmetrical position by a time-sharing system
Furthermore, another preferred mode of the digital filter according to the invention multiplexes two series of serial data and converts them into one series of serial data, wherein the serial data are inputted into a plurality of stages of delay elements having a folded structure, the respective outputs of a pair of delay elements in the symmetrical position are distributed by time-sharing via a selector, the two series of data are processed in parallel so that the independency of the respective series are not spoiled, and are finally separated into data of the respective series.
Thereby, the number of a plurality of stages of delay elements becomes 1-xth times the conventional number, the operating frequency is lowered to two-xth times, and the number of digital filter coefficients, multipliers and adders also become one-xth times the conventional number.
Furthermore, in another preferred mode of the digital filter according to the invention, the construction of a selector is devised, and data orthogonal to each other are used as two series of data to be multiplexed. The data orthogonal to each other are, for example, I signal data and Q signal data which are used in digital radio transmission.
Furthermore, in another preferred mode of the digital filter according to the invention, one of the two series of data separated and outputted from the digital filter is provided with a phase adjusting circuit for adjusting the phase.
Furthermore, another preferred mode of the digital filter according to the invention is provided with a selector which selects and outputs either data passed through the phase adjusting circuit or data not passed therethrough. By controlling the selector, it is possible to selectively output QPSK (Quadrature Phase Shift Keying) modulated signals and OQPSK (Offset Quadrature Phase Shift Keying) modulated signals.
Furthermore, in another preferred mode of the digital filter according to the invention, two types of digital filter coefficients are prepared, corresponding to the two series of multiplexed data, and the digital filter coefficients are selectively used. It is preferable that two types of digital filter coefficients are adequately rewritten.
Furthermore, in another preferred mode of the digital filter according to the invention, the frequency of a clock used in the digital filter is made variable. In this case, a timing adjusting circuit may be provided, which is able to adjust the output timing of two series of data outputted from the digital filter.
With the invention, a novel and small-sized digital filter can be achieved, which allows for suppression of power consumption, and a processing feature for interpolating digital signals x times, wherein x is a natural figure of 4 or more.
Furthermore, a communication apparatus according to the invention is a communication apparatus provided with the abovementioned x-time interpolation digital filter. The digital filter can be used to limit the band of transmission signals before digital-analog conversion.
Furthermore, in one of the preferred modes of the communication apparatus according to the invention, the multiplying coefficients in the digital filter can be kl renewed in real time, the gain of the filter is adequately adjusted, and the gain difference of the two series of transmission signals can be reduced.
Furthermore, in another preferred mode of the communication apparatus according to the invention, the conformity with other circuits can be increased by adequately selecting the operating frequency of the digital filter.
With the invention, a high-performance, high-speed, novel, and small-sized communication apparatus can be achieved, which is used for digital mobile transmission at suppressed power consumption.
REFERENCES:
patent: 5335194 (1994-08-01), Clayton et al.
patent: 5528527 (1996-06-01), Iwata et al.
patent: 5621404 (1997-04-01), Heiss et al.
patent: 6134569 (2000-10-01), Kot
patent: 55109024 (1980-08-01), None
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An English language abstract of JP 55-109024.
An English Language abstract of JP 61-107808.
An English language abstract of JP 8-162906.
An English Language abstract of JP 8-84048.
Greenblum & Bernstein P.L.C.
Mai Tan V.
Matsushita Electric - Industrial Co., Ltd.
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