Digital filter circuit

Details Digital filter circuit Digital filter circuit

1991-05-28

1993-06-22

Nguyen, Long T.

Boots, shoes, and leggings

G06F 1531

Patent

active

052220354

ABSTRACT:
When each sample is expressed by digital signals of 8 bits, 8 bits constituting each of the digital signals are divided into data of upper 5 bits including the most significant bit, and data of lower 4 bits including the least significant bit. These two data are respectively inputted to two filter circuit units, and are simultaneously subjected to a filtering process separately. Outputs of these two filter circuit units are inputted to an adder. In the adder, the output of the filter circuit unit being data of upper 5 bits subjected to a filtering process is weighted by a factor of 2 to the 4th power, and the weighted output is added to the output of the other filter circuit unit. The results of adding are outputted from the adder as signals obtained by the original digital signals of 8 bits subjected to the filtering process. Since the number of bits of individual data is made small by the division, the operation speed of computing elements and the number of times of recursive or multiple uses of computing elements are increased so that the circuit scale of the entire filter circuit can be reduced.

REFERENCES:
patent: 4323980 (1982-04-01), Houdard et al.
patent: 4484299 (1984-11-01), Lambourn et al.
patent: 4618941 (1986-10-01), Linder et al.
patent: 4644488 (1987-02-01), Nathan
patent: 4802111 (1989-01-01), Barkan et al.
patent: 5050119 (1991-09-01), Lish
Wallace, "A Suggestion for A Fast Multiplier", IEEE Trans. on Electronic Computers, vol. 13, No. 1, Feb. 1964, pp. 14-17.

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