Digital filter circuit

Registers – Transfer mechanism – Traveling pawl

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Details

235152, G06F 1534, G06F 752

Patent

active

040341976

ABSTRACT:
In U.S. Pat. No. 3,906,199, issued to R. B. Kieburtz and K. V. Mina on Sept. 16, 1975, limit cycle noise is reduced in a second order recursive digital filter by a circuit which randomly inhibits the rounding signal in one of the digital multipliers disposed in the filter. It has been found, however, that in certain instances, this approach results in even longer transients.
In accordance with the present invention, random inhibiting is constrained to instances in which limit cycle noise is reduced, by monitoring, with suitable logic circuitry, the signals present in the various feedback loops of the filter. Generally, it has been found that the inhibiting circuit should be allowed to operate only if D.sub.1 and D.sub.2 satisfy predetermined magnitude and polarity relationships, where D.sub.1 .ident. a version of the filter output signal Y(n) that is removed in time by one sample interval, and D.sub.2 .ident. a version of the filter output signal Y(n) that is removed in time by two sample intervals.
In accordance with another aspect of the invention, DC and half sampling rate limit cycles are eliminated by monitoring three consecutive values of D.sub.1 or, alternatively, the present values of Y(n), D.sub.1 and D.sub.2. If the same magnitudes are detected, the magnitude of the next D.sub.1 is reduced by one.

REFERENCES:
patent: 3749895 (1973-07-01), Kao
patent: 3906199 (1975-09-01), Kieburtz et al.
H. Butterwick, "Suppression of Parasitic Oscillations . . . Rounding Arithmetic", special reprint from AEV, band 29, 1975, pp. 371-374.
M. Buttner, "Some Experimental Results . . . In Recursive Digital Filters", NTZ-Aufsatze NTZ 28, (1975), H. 11, pp. 402-406.

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