Digital filter arrangement having memory means with addressable

Details Digital filter arrangement having memory means with addressable Digital filter arrangement having memory means with addressable

1982-03-09

1984-11-20

Malzahn, David H.

Boots, shoes, and leggings

G06F 1531

Patent

active

044842996

ABSTRACT:
A digital filter arrangement in which an input pulse stream is entered in consecutive non-overlapping groups into a first shift register. The contents of the first register are transferred in parallel into a plurality of shift registers. Bits are read-out from selected positions of the plurality of shift registers to form address words for individual read-only memories (ROM). Each ROM has stored therein weighted impulse response outputs which are read out in accordance with the address words. The outputs from the ROM's are added in logic circuitry and the combined output is fed into a latch. The contents of the latch are entered into a buffer from where they are read out serially. If the input clock rate is 28 MHz and the plurality of shift registers number eight, the plurality of shift registers, the ROM's and the logic circuitry operate at 3.5 MHz.

REFERENCES:
patent: 4146931 (1979-03-01), Delforge
patent: 4374426 (1983-02-01), Burlage et al.
Schroder, "High Word-Rate Digital Filters with Programmable Table Look-Up" IEEE Trans. on Circuits & Systems vol. CAS-24, No. 5, May 1977, pp. 277-279.
Peled et al., "A Now Hardware Realization of Digital Filters" IEEE Trans. on a Coustics, Speech & Signal Processing Assp-22, No. 6, Dec. 1974, pp. 456-462.

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