Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Patent
1998-10-14
2000-11-21
Mai, Tan V.
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
708316, G06F 1717, G06F 1710
Patent
active
061516139
ABSTRACT:
A digital filter receives signals from each stage of a MASH delta-sigma modulator and filters noise components from the signals prior to combination as a single sequence of values decimation. Each stage of the MASH delta-sigma modulator provides an output sequence of one-bit, binary values, which are then filtered to remove high-order, out of band quantization noise. After filtering, the output sequences are then combined through a cascade-combiner, which may be similar to the pre-processing stage of a MASH delta-sigma modulator architecture. The digital filter processes signals of each stage separately. Consequently, the digital filter does not perform multiplication of two, multi-bit values. Multiplication of two values, the first of which is a one-bit, binary value, may be implemented with a multiplexer selecting either the second value or a zero value based on the first one-bit, binary value (i.e., logic 1 or 0, respectively). Duplicate FIR filters, or a single FIR filter with bit-interleaving by a multiplexer, master-slave delay chain and demultiplexer controlled by system clock transitions, may be used to process the sequences on a single bit basis, replacing multi-bit multipliers of the digital filter with multiplexers. Alternatively, the FIR filter may be implemented with a multiplexer, master-slave delay chain, ROM look-up table and demultiplexer if bit interleaving is employed.
REFERENCES:
patent: 5181033 (1993-01-01), Yassa et al.
patent: 5696708 (1997-12-01), Leung
patent: 5949361 (1999-07-01), Fischer et al.
patent: 6028544 (2000-02-01), Zarubinsky et al.
Hughes Ian M.
Lucent Technologies - Inc.
Mai Tan V.
Mendelsohn Steve
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