Television – Synchronization – Automatic phase or frequency control
Reexamination Certificate
2001-08-30
2004-11-23
Lee, Michael H. (Department: 2614)
Television
Synchronization
Automatic phase or frequency control
C348S470000, C348S536000
Reexamination Certificate
active
06822692
ABSTRACT:
The invention relates to a digital filter for filtering a digital input signal, in particular QAM- and QPSK-modulated input signals.
In many technical applications, there is a need for signal receivers which can process both digital input signals with a high input clock frequency and sampling frequency and input signals with a low input clock frequency and sampling frequency. An example of this is a digital television receiver (DVB) which can receive both a high-frequency 4 QAM signal which is subject to noise and which is transmitted via satellite, and a low-frequency relatively noise-free 256 QAM signal which is transmitted via cable.
FIG. 1
shows a block circuit diagram of a television receiver according to the prior art. The television receiver receives the 4 QAM-modulated signal which is subject to noise and is transmitted by a satellite via a first input Esat, and the television receiver receives the relatively noise-free 256 QAM-modulated cable input signal via the second input E
cable
. The satellite input signal has, for example, a symbol rate f
symbol
of 24 megasymbols per second, each symbol being 4 QAM-modulated, i.e. having two bits. The 256 QAM-modulated cable input signal has, for example, a symbol rate f
symbol
of 6 megasymbols per second, each data symbol having a data bit width of 8 bits.
The following applies for the input clock frequency of the input signal and/or for the input data rate DR:
DR=f
symbol
·symbol bit width (1)
to which the following applies:
4 QAM
256 QAM
(satellite)
(cable)
f
symbol
24
M
symb
sec
6
M
symb
sec
Symbol bit width
2 bit
8 bit
DR
48
Mbit
sec
48
Mbit
sec
F
clock
48 MHz
12 MHz
For the high-frequency satellite signal (4 QAM), circuits with a high sampling frequency and simple filters with a low filter length are used in the receiver, while for the low-frequency cable signal (256 QAM) circuits with a low sampling frequency and complex filters with a high filter length are used in the receiver. In the example shown in
FIG. 1
, the filter A has, for the high-frequency satellite input signal, a filter length N
1
which is significantly smaller than the filter length N
2
of the digital filter B for the cable input signal. In the conventional receiver, the output signals of the two digital filters A, B are fed to a controllable switching device S which in each case outputs an output signal of a filter A, B to a downstream data processing unit DV for further data processing. A television receiver TV is connected to the output of the data processing unit DV.
The digital filters A, B shown in
FIG. 1
typically each have the circuit structure shown in FIG.
2
. The two digital filters A, B are each composed here of registers Z
1
, Z
2
to Zn which are connected in series and whose outputs are connected to multipliers M
1
to Mn for multiplication by filter coefficients K
1
to Kn. The outputs of the multipliers M
1
to Mn are connected to adders A
1
to An-
1
which are connected in series to one another. The registers Z
1
to Zn are clocked with a sampling frequency f
clock
, the following applying:
f
clock
≧f
symbol
(3)
For f-clock-symbol, the digital filter A for the high-frequency satellite signal thus has a clock frequency f
TA
of 48 MHz, and a clock frequency f
TB
of 12 MHz is sufficient for the filter B for the low-frequency cable input signal.
In order to minimize the expenditure on circuitry, the filter lengths of the two digital filters A, B depend on the chip clock frequency f
chip
and on the clock frequency f
clock
:
n
=
f
chip
f
clock
(
4
)
Given a chip clock frequency f
chip
of, for example, 240 MHz, with the values given in the table for the clock frequencies f
clock
the filter lengths for the two digital filters A, B, as illustrated in
FIG. 1
, are obtained as:
n
A
=
240
MHz
48
MHz
=
5
n
B
=
240
MHz
12
MHz
=
20
(
5
)
The filter B for filtering the cable input signal has a large filter length n=20, so that the digital filter B can be implemented with only a very high degree of expenditure on circuitry. As is apparent from
FIG. 2
, such a filter B requires 20 registers and 20 multiplication circuits M
1
to M
20
, the multiplier circuits M
1
to M
20
in particular requiring a high degree of expenditure on circuitry.
A further disadvantage of the receiver circuit shown in
FIG. 1
according to the prior art is that the two digital filters A, B have permanently predefined filter lengths, n, and thus are inflexible toward changes in the type of modulation.
The object of the present invention is therefore to provide a digital filter for filtering a digital input signal which is suitable for filtering digital input signals which are modulated in different ways, and which can be implemented with a low degree of expenditure of circuitry.
This object is achieved according to the invention by means of a digital filter having the features disclosed in patent claim
1
.
The invention provides a digital filter for filtering a digital input signal with a variable filter length, it being possible to switch over the filter length of the digital filter as a function of a variable input clock frequency of the digital input signal without the ratio of input clock frequency to an output clock frequency of the filtered digital output signal which is output by the digital filter changing.
The digital filter according to the invention provides the advantage that it always supplies an output signal which has a constant output clock frequency and which can be fed directly to a further data processing means without adaptation circuits.
The digital filter is preferably of modular design composed of at least one digital filter module.
Here, the digital filter module is preferably composed of a filter coefficient circuit for outputting filter coefficients to a multiplier device which multiplies the filter coefficients output by the filter coefficient circuit by an input data signal which is present at a first input of the digital filter module,
an adder circuit for adding the signal output by the multiplier device to a demultiplexer output signal which is output by a demultiplexer output of a first demultiplexer, and a register circuit which is composed of a plurality of registers which are connected in series, the outputs of the registers each being connected to an input of the first demultiplexer.
The digital filter module according to the invention merely requires a multiplier device, and can thus be implemented very easily in terms of circuitry.
In a first embodiment of the digital filter according to the invention, the filter modules are connected in parallel with one another.
In an alternative embodiment of the digital filter according to the invention, the digital filter modules are connected in series.
The digital filter modules are preferably controlled by a central control circuit.
The digital filter module according to the invention preferably has a controllable switch for reading out the demultiplexer output signal of the first demultiplexer to a signal output of the digital filter module.
The digital filter module also preferably has a controllable resetting circuit for resetting the demultiplexer output signal at the demultiplexer output of the first demultiplexer.
In a particularly preferred embodiment, the digital filter module has a second demultiplexer with two demultiplexer inputs and a demultiplexer output, the first demultiplexer input being connected to a second input of the digital filter module, the second demultiplexer input being connected to an output of the resetting circuit and the demultiplexer output of the second demultiplexer being connected to the adder circuit.
In a first embodiment of the digital filter module according to the invention, the filter coefficient circuit is a filter coefficient generating circuit for generating the filter coefficients.
In an alternative embodi
Lee Michael H.
Tran Trang U.
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