Digital filter

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Unwanted signal suppression

Reexamination Certificate

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Details

C327S553000

Reexamination Certificate

active

06657482

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The technical field of the present invention relates to that of a digital filter in which an input signal is filtered using a feedback path configured with delay device, generating an output signal with a frequency characteristic having a predetermined time constant.
2. Description of the Related Art
Recent tuner designs capable of receiving and demodulating AM or FM broadcasts have increasingly incorporated various digital signal processing. In a digitized tuner, a digital filter is used to remove undesired frequency components from the input signal. To perform the level detection of the input signal for example, a low-pass filter for removing modulation components can be formed from a digital filter. Furthermore, by appropriate adjustment of an AGC amplifier gain for IF signals based on the level detection output by the digital filter, a stable detection output can be maintained regardless of variations in the receiving field strength of the tuner.
However, the receiving field strength of a tuner may rapidly change with time. As an example, the receiving field strength of an automotive tuner rapidly increases or decreases when it enters or exits a place such as a tunnel where reception of radio waves is difficult. If the time constant of the low-pass filter used for the level detection of the AGC amplifier is too large, it is possible that the slowed response time cannot follow such rapid changes in the receiving field strength. This can lead to insufficient control of the AGC amplifier gain, resulting in a deterioration of the detection output. Conversely, if the time constant of the low-pass filter is small, although the response time is reduced, undesired modulation components cannot be removed. Thus, the low-pass filter for use with the level detection of the AGC amplifier in a tuner is preferably configured so that the time constant can be switched between a large value and a small value. Therefore, if the receiving field strength varies rapidly, the time constant can temporarily be set to a small value so that the output of the low-pass filter can be followed, thereby ensuring satisfactory operation of the AGC amplifier.
Changing the time constant of the low-pass filter (as described above) in an analog tuner can easily be configured by switching the connection paths corresponding to the two time constants determined by circuit constants. Similarly, if a digital filter is used, the time constant is determined by the coefficient of a multiplier, and thus a comparable configuration may be achieved in which the time constant can be switched by changing the connection of the two paths for which different coefficients are established.
However, as an example, an IIR type digital filter comprises a feedback path including a delay unit. One problem with such a filter is ensuring successful matching with the delay unit at the timing when switching the time constant. That is, in the IIR type digital filter, if the coefficient of the multiplier changes when the time constant is switched, the data in the delay unit needs to change for matching therewith. However, old data is held in the delay unit just after the switching and thus mismatching occurs. Consequently, the output of the digital filter temporarily becomes discontinuous at the time of switching. This results in the further problem of noise caused in the detection output when switching the time constant if the digital filter is applied to the level detection of the AGC amplifier.
SUMMARY OF THE INVENTION
Accordingly, the present invention has been accomplished in view of such problems, and aims to provide a digital filter which includes a configuration for switching the time constant, and which can ensure a stable operation without producing noise at the instant of switching the time constant.
The above object of the present invention can be achieved by a digital filter for forming a feedback path including a delay device, applying a filter operation to an input signal, giving a frequency characteristic having a predetermined time constant, and generating an output signal, provided with: a time constant switching device having operation device for implementing time constants in at least two stages, and selecting the connection of said operation device corresponding to a preset time constant to perform time constant switching; a timing determination device for determining the timing for correcting the output of said delay device according to the switching direction of time constant when said time constant switching is performed; and a correction device for correcting the output of said delay device to suppress variations in said output signal in said determined timing.
In accordance with this invention, the time constant for a digital filter can be switched in two or more steps, and if a time constant is set, the connection of operation device is selected, and the digital filter operates with a desired time constant. Accordingly, depending on the state of variation in the input signal, the time constant of the digital filter can be optimized to secure a balance between stability and follow-up ability. Furthermore, when the time constant is changed, the timing for correcting the output of the delay device included in the feedback path is determined, and according to the switching direction of the time constant, the output of the delay device is appropriately corrected with the determined timing. As a result, by correcting the data mismatching in the delay device at the time of switching the time constant, noise due to the digital operation can be prevented.
As described above, in accordance with the present invention, a configuration for switching the time constant is provided in a digital filter, and the delay device in the feedback path is corrected so as to suppress the variation in the output signal at the time of switching the time constant, so a stable operation can be secured without producing noise due to the filter operation.
In one aspect of the digital filter of the present invention, said time constant switching device has a first selecting device inserted inside said feedback path, and a second selecting device inserted outside said feedback path, said first selecting device and said second selecting device provided with: two or more multipliers for which coefficients corresponding to different time constants are respectively set; and a selector for selectively connecting said multiplier matching said preset time constant.
In accordance with this invention, in addition to the action of the invention as set forth in claim 1, there is provided a configuration in which the first selecting device and the second selecting device are respectively inserted inside and outside the feedback path of the digital filter, and two or more multipliers and selectors are provided in each selecting device to enable the connection corresponding to the established time constant.
Thus, it is only needed to select the connection of the two selectors to change the time constant, and moreover, a desired time constant in the digital filter can be selected without performing complicated processing.
In another aspect of the digital filter of the present invention, said timing determination device generates a timing control signal according to said switching direction of time constant in said determined timing.
In accordance with this invention, in addition to the action of the invention as set forth in claim 1, the correction of the output of the delay device is defined according to the time constant signal, so the data mismatching in the delay device can automatically be corrected without the need for a complex determination.
In further aspect of the digital filter of the present invention, said timing control signal generates a pulse for one clock from said determined timing based on the clock supplied to said delay device.
In accordance with this invention and in addition to the action of the invention as set forth in claim 3, the timing for correcting the output of the delay devic

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