Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1999-03-10
2001-10-09
Malzahn, David H. (Department: 2121)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
06301595
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a digital filter and, more particularly, to a technique to prevent the occurrence of a limit cycle in an Infinite Impulse Response (IIR) digital filter.
2. Description of the Prior Art
It is known that IIR (recursive) digital filters, the so-called limit cycle phenomenon, an oscillation component is output that is unrelated to an input signal, occurs when an amplitude level if the input signal becomes lower than a certain input level (which is called a critical input level). The amplitude level of the output at that time is called a dead band amplitude level.
When the limit cycle occurs, the oscillation component unrelated to the input signal is output, which is observed as a kind of an oscillation phenomenan. The oscillation component may cause a malfunction of a unit disposed after a section of the digital filter. In the case of voice communication systems, the oscillation component gives an unnatural impression to recivers.
In addition, since a kind of oscillation signal is output where the limit cycle occurs, it is sometimes difficult to discriminate between a target signal and the oscillation signal caused by the limit cycle when the signal is processed at a unit disposed after a section of the digital filter.
It is thought that this limit cycle phenomenon is caused partly by an aritmethic operation part of the digital filter that adopts a finite word length. It is also known that increasing arithmetic word length, i.e. reducing quantizing steps, make it possible to reduce the dead band amplitude level or prevent the occurence of the limit cycle.
However, increasing the arithmetic word length in the digital filter for prevention of the limit cycle disadvantageously leads to increase in size and complexity of the digital filter.
Setting the coefficient of the digital filter at a value at which no limit cycle occurs results in imposing limitations on the characteristics of the digital filter.
In order to prevent the amplitude level of input signal of the digital fiber from becoming lower than the critical input level, a technique of adding a tone signal having an amplitude above the critical input level to the input signal of the digital filter is known. The addition of the tone signal can prevent the occurence of the limit cycle. However, when the frequency of the tone signal is set to be within a passband of the digital filter, it is necessary to remove the tone signal at the output side.
On the other hand, when the frequency of the tone signal is set to be within a rejection band of the digital filter, the need for removing the tone signal can be eliminated. However, in the case of the digital filter being formed in the cascade connection form, the tone signal added at the input side of the digital filter is suppressed in the 1st-stage process of the digital filter, so that it is still necessary to add tone signals thereafter, for prevention of the limit cycle. Thus, tone signal generating means are necessary for the required number of stages of the filter.
Another technique of adding a noise signal formed of random data, which is called the dither, to the input signal is also known. This technique may be used instead of adding the tone signal to the input signal. For example, Japanese Laid-open Utility Model Publication No. Sho 56 (1981)-176528 and Japanese Laid-open Patent Publications No. Hei 05 (1993)-090900 and No. Hei 5 (1993)-110384 disclose the technique of adding separately generated random data (dither) to the input signal, to prevent the occurence of the limit cycle.
The Japanese Laid-open Patent Publication No. Hei 5 (1993)-110384 discloses a technique wherein when the input signal is detected to be zero, a level of the dither to be added is increased and then the increased level of the dither is added to the input signal.
However, this technique of generating the dither separately requires an increased amount of arithmetic in an arithmetic unit, such as the CPU, thereby increasing the load on the arithmetic unit. Otherwise, additional specialized hardware may be required.
Although a signal as random as possible, like white noise, is desirable for the dither, in general, an M sequence signal is used as the artificially generated dither. The M sequence signal is used as the artificially generated dither. The M sequence signal however canoot be regarded as equivalent to white noise without extending its period to a considerable extent. In the case the period of the M sequence signal is short, a periodic component caused by the short period is included in the signal. If the frequency of the period component is within the passband of the digital filter, then it may give an unnatural impression to receivers, as is the case with the limit cycle occuring. When the period is extended to prevent this problem, there arises a problem that an amount of arithmetic in the arithmetic unit, such as the CPU, is further increased to that amount, or additional specialized hardware is required.
SUMMARY OF THE INVENTION
Accordingly, the present invention has been made, with the aim of providing the technique of preventing the limit cycle, with a simplified structure, for the IIR digital filter adopting arithmetic operation part of finite word length.
A digital filter according to the invention comprises an IIR digital filter; an extracting means to extract only a specified number of bits at a low end of an input signal and to output the extracted signal; an amplifying means to amplify the extracted signal at an amplitude level to a level larger than a critical input level in which a limit cycle occurs in the IIR digital filter and to output the extracted signal as amplified; and an adding means to add the input signal and the extracted signal as amplified and to input the added signal into the IIR digital filter.
Further, a digital filter according to the invention comprises an IIR digital filter; an extracting means to extract only a specified number of bits at a low end of an input signal and to output the extracted signal; an amplifying means to amplify the extracted signal at an amplitude level to a level larger than a critical input level in which a limit cycle occurs in the IIR digital filter and to output the extracted signal as amplified; a level comparing means to detect an amplitude level of the input signal and to compare it with the critical input level; and an adding means to add the input signal and the extracted signal as amplified and to input the added signal into the IIR digital filter, when the amplitude level of the input signal is smaller than the critical input level.
Preferably, the specified number of bits to be extracted by the extracting means should be two bits or more.
REFERENCES:
patent: 3749895 (1973-07-01), Kao
patent: 4920507 (1990-04-01), Takeda
patent: 5148382 (1992-09-01), Kishi
patent: 5894428 (1999-04-01), Harada
patent: 56-176528 (1981-05-01), None
patent: 5-90900 (1993-04-01), None
patent: 5-110384 (1993-04-01), None
Icom Incorporated
Malzahn David H.
Wenderoth , Lind & Ponack, L.L.P.
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