Digital FIFO memory

Details Digital FIFO memory Digital FIFO memory

1988-08-15

1990-02-13

Fears, Terrell W.

Static information storage and retrieval

Addressing

365 73, 365238, G11C 1300

Patent

active

049012860

ABSTRACT:
A digital FIFO memory is disclosed which is formed by a memory cell array (zf) comprising of n signal channels (b1 . . . bn) each containing m memory cells (c..1, c..2, c..m-1, c..m) are first, second, and mth clock drivers (tt1, tt2, ttm-1, ttm), respectively, which are controlled by a basic clock signal (g1) and further signals. Thus FIFO memory makes it possible to pass an input data stream arriving at an input data rate (g2) through the FIFO memory in such a way that the output data stream appears at the output (da) at an output data rate (g3) momentarily different from the input data rate (g2). On a time average, however, the two data rates are equal, so that data can be written into and read from the FIFO memory simultaneously at different rates.

REFERENCES:
patent: 3708690 (1973-02-01), Paivinen
patent: 3745535 (1973-07-01), DeKoe et al.
The Stacking Register--A Simultaneous Input/Output Buffer; G. Philokyprou and A. Zacharacopoulos; Nuclear Instruments and Methods 65 (1968) 202-204.

Affiliated with

Also associated with

Rating

Digital FIFO memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Digital FIFO memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital FIFO memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1173894