Coded data generation or conversion – Analog to or from digital conversion – Multiplex
Reexamination Certificate
2002-07-02
2004-11-30
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Multiplex
C341S144000
Reexamination Certificate
active
06825785
ABSTRACT:
REFERENCE TO COMPUTER PROGRAM LISTING APPENDIX
A Computer Program Listing Appendix is filed herewith on compact disk, the material of which is hereby incorporated by reference in its entirety. The compact disk is submitted in duplicate (labeled COPY 1 and COPY 2) and each of the two identical disks contains a file named “dacExpander.txt” having a file size of 28,728 bytes (29 kb) and having a file creation date of Apr. 17, 2002.
COPYRIGHT NOTICE
A portion of the disclosure of this patent document, including certain figures and the Computer Program Listing Appendix, contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the U.S. Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.
BACKGROUND
1. Field of the Invention
This invention relates to the generation of multiple control signals, and particularly to those useful for controlling a sub-varactor array of a voltage controlled oscillator such as in a phase-locked loop circuit.
2. Description of Problem to be Solved and Related Art
Phase locked loops (PLLs) have been known and studied for quite some time. Initially they were very expensive to implement, and found use in only the most technically-demanding and/or cost-insensitive applications. However, as the cost of integrated circuit technology has decreased over the years, and as the performance capability of such integrated circuit technology has increased, today PLLs are extremely inexpensive to implement and are found in wide use in many applications.
Within a traditional PLL, a filter block is frequently included to low-pass filter an output signal of a phase/frequency detector to generate a control signal for a voltage controlled oscillator (VCO) in order to influence the frequency (and hence the phase) of the VCO output signal. The filter block is often implemented using a charge pump and one or more loop filter capacitors, as is well known in the art. Such loop filter capacitors may be required to be very large for the PLL to exhibit acceptable peaking behavior in its frequency response.
Moreover, for certain applications, the loop bandwidth may need to be extremely low, including as low as 100 Hz. Achieving a bandwidth this low is very difficult using traditional techniques, and may require large capacitors which are difficult to integrate onto an integrated circuit without requiring large amounts of die area. For this reason, a loop filter capacitor is frequently provided externally. But such an external capacitor adds an additional complexity to board layout, and introduces noise susceptibility on the extremely critical loop filter node within the PLL.
SUMMARY OF THE INVENTION
Digital techniques for implementing a PLL loop filter may be utilized to digitally integrate a digital phase error signal to yield a digital signal representing the integrated phase error signal, and thereby reduce substantially the capacitors which must be integrated of are desired. But such a digital signal may still need to be converted to one or more analog signals to control a VCO. Improved conversion circuits and techniques are still greatly desired.
An exemplary PLL circuit includes a VCO responsive to a plurality of sub-varactor control signals. A digital loop filter for the PLL digitally generates a varactor control word, which is digitally expanded into a plurality of digital values, each of which is conveyed to a corresponding one of a plurality of DACs. In certain embodiments a multiplexer is configured to respectively convey or steer the DAC output signals to a group of sub-varactor control signals according to the varactor control word, and to drive remaining sub-varactor control signals to either the full-scale high value or the full-scale low value of the DAC outputs. In other embodiments, a dedicated DAC may be provided for each sub-varactor control signal and a multiplexer not utilized.
Preferably each of the one or more DACs include a hybrid first order/second order sigma-delta modulator to advantageously achieve the lower noise properties of a second order modulator, but also achieve full-scale output range of a first order modulator. When the analog output voltage of a DAC is at a value either at or near the top or bottom voltage rail (i.e., at or near the desired output range), the sigma-delta modulator is preferably operated as a first order modulator to achieve a full-scale output range, but otherwise the sigma-delta modulator is configured to operate as a second order modulator to achieve the lower noise properties. In certain embodiments, each of the DACs preferably includes an NRZ-to-RZ coder circuit and a linear filter circuit.
In an exemplary embodiment of the invention, 128 control signals are generated using only 8 DACs. The varactor control word may be used to determine which 8 of the 128 control signals are coupled by a multiplexer to the DACs, as well as the digital value communicated to each DAC. The multiplexer preferably couples each of the remaining control signals “below” the selected group to one of the DAC voltage rails, and couples the remaining control signals “above” the selected group to the other of the DAC voltage rails. As the varactor control word changes sufficiently in value, a DAC from one end of the selected group of control signals may be “rolled” or switched to drive a new control signal at the other end of the newly selected group of control signals. In an exemplary embodiment, at most only four of the eight DACs generate intermediate voltages between the DAC voltage rails. When a DAC is about to be rolled, its output is already at one of the two DAC voltage rails, and the control signal coupled thereto may be instead coupled by the multiplexer directly to the DAC voltage rail without glitching the control signal. Then the DAC may be driven to the other voltage rail, its output allowed to settle, and then coupled to a new control signal at the other end of the newly selected group of 8 control signals
In other embodiments the analog value of each control signal may be determined by a varactor control word, but the selection of which control signals are driven by DACs or driven directly by the multiplexer to a voltage rail may be determined by another control word. For example, the varactor control word may be generated by adding a PLL loop filter feed-forward value to a PLL loop filter integrating path value, whereas the selection may be based only upon the PLL loop filter integrating path value, which is a lower frequency component of the varactor control word.
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Garlepp Bruno W.
Huang Yunteng
Silicon Laboratories Inc.
Wamsley Patrick
Zagorin O'Brien & Graham LLP
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