Digital error correction system for subranging analog-to-digital

Details Digital error correction system for subranging analog-to-digital Digital error correction system for subranging analog-to-digital

1990-06-04

1991-09-10

Scott, J. R.

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

341161, 341120, 341118, H03M 144, H03M 110

Patent

active

050477722

ABSTRACT:
A general architecture to correct conversion errors of a multi-stage, pipelined subranging analog-to-digital (A/D) converter includes cascaded stages, each stage generating a binary conversion signal representing the nearest quantized level below that of the analog input signal and a residual analog signal applied to the next conversion stage. The binary conversion signal from each stage addresses individual or common look-up tables providing a compensated binary signal selected to compensate for nonidealities of the A/D converter components. The compensated binary signals from the look-up tables provide a corrected output signal when summed together. A simple method of calibration for the A/D converter makes use of a least-mean-squared adaptation algorithm. The A/D converter accommodates practical circuit nonidealities such as component mismatching, gain error and voltage offsets, and handles high levels of amplifier nonlinearity. The architecture is applicable to any subranging converter with arbitrary numbers of stages and bits per stage.

REFERENCES:
patent: 4612533 (1986-09-01), Evans
patent: 4894656 (1990-01-01), Hwang et al.
patent: 4903023 (1990-02-01), Evans et al.
patent: 4903026 (1990-02-01), Tiemann et al.
patent: 4908621 (1990-03-01), Polonio et al.
patent: 4947168 (1990-08-01), Myers
A. Dingwall et al., "An 8-MHz CMOS Subranging 8-bit A/D Converter," IEEE J. Solid-State Circuits, vol. SC-20, pp. 1138-1143, Dec. 1985.
S. Lewis et al., "A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter," IEEE J. Solid-State Circuits, vol. SC-22, No. 6, pp. 954-961, Dec. 1987.
S. Boyacigiller et al., "An Error Correcting 14b/20 .mu.s CMOS A/D Converter," ISSCC Dig. Tech. Papers, pp. 62-63, Feb. 1981.
B. Widrow et al., "Adaptive Signal Processing", Prentice-Hall, Inc., pp. 99-114, (1985).

Affiliated with

Also associated with

Rating

Digital error correction system for subranging analog-to-digital does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Digital error correction system for subranging analog-to-digital, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital error correction system for subranging analog-to-digital will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-542962