Digital electronic still-video camera and method of controlling

Details Digital electronic still-video camera and method of controlling Digital electronic still-video camera and method of controlling

1995-06-05

1996-07-23

Greening, Wendy R.

Television

Camera, system and detail

Combined image signal generator and general image signal...

348220, 358310, 358320, 3589091, H04N 5228, H04N 989

Patent

active

055394558

ABSTRACT:
Power consumption in a still-video camera at playback of pixel data is suppressed. Image data indicative of each pixel is written in a frame memory in synchronization with a prescribed clock frequency (14.32 MHz) in a photographic mode. At the time of playback, a clock signal whose frequency (7.16 MHz) is half that of the clock signal in the photographic mode is applied to each circuit block of the camera. The value of the count in an H-direction address counter for outputting address data in the horizontal direction is doubled in a doubler circuit. Data representing the doubled value of the count is applied to a frame memory as horizontal-direction address data. As a result, the frame memory outputs pixel data that is thinned out every other pixel, and the outputted data is sent to a playback processing circuit.

REFERENCES:
patent: 4584613 (1986-04-01), Amari
patent: 4633330 (1986-12-01), Yamamitsu
patent: 4774594 (1988-09-01), Urata
patent: 4837628 (1989-06-01), Sasaki
patent: 4862292 (1989-08-01), Enari
patent: 4984094 (1991-01-01), Emori
patent: 5206730 (1993-04-01), Sakai
patent: 5229862 (1993-07-01), Takahashi

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