Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Converging with plural inputs and single output
Reexamination Certificate
2001-08-24
2002-11-12
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Gating
Converging with plural inputs and single output
C327S404000, C326S050000
Reexamination Certificate
active
06480054
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to digital electronics, and more particularly to a digital electronic circuit for use in logic design.
BACKGROUND
Digital electronic circuits are used in virtually every modern electronic system, such as computers, watches and telephones. Under continuous pressure from users for increased functionality from electronic systems, designers and manufacturers of digital electronic circuits constantly strive to reduce the size and increase the performance of their circuits. Even modest gains in the density and/or performance of a circuit become substantial if the circuit is repeated many times within a system.
Traditionally, digital logic functions have been implemented with a plurality of discrete logic circuits or gates including AND gates, OR gates, NAND gates, NOR gates, etc., each constructed of several transistors. Subsequently, it was discovered that certain special purpose digital circuits such as multiplexers could be used to implement digital logic functions using fewer transistors than with discrete gates. In addition, improved multiplexers were developed which used even fewer transistors. These multiplexers, commonly known as “Transmission Gate” multiplexers, are described in my prior U.S. Pat. Nos. 5,040,139, 5,162,666, 5,200,907, and 5,548,231, the disclosures of which are herein incorporated by reference.
FIG. 1
shows an exemplary 4:1 transmission gate multiplexer
10
connected to an output driver
11
. Transmission gate multiplexer
10
includes three 2:1 transmission gate multiplexers
12
a-c
connected in a serial cascading or hierarchical configuration, as described in my U.S. Pat. No. 5,162,666. The 2:1 transmission gate multiplexer (hereinafter referred to as a TGM) is the basic building block of larger transmission gate multiplexer systems. Each TGM is configured to receive two input signals I
i
and I
i+1
, and a control signal S
i
. The TGM selects one of the two input signals based on the logic value of control signal S
i
. The selected input signal is transmitted to the output of the TGM, while the input signal not selected is blocked. The output of each TGM is connected to one of the inputs of the next higher TGM until final TGM
12
c
is reached. Thus, one of N input signals can be selected for transmission using N−1 TGM's connected in a hierarchical arrangement. The output of final TGM
12
c
typically is connected to an output driver
11
which is adapted to charge and discharge relatively large capacitive loads. The signal from output driver
11
is designated Q in FIG.
1
.
FIG. 2
shows the construction of a typical TGM and output driver using Complimentary Metal Oxide Semiconductor (CMOS) technology. TGM
12
c
includes two transmission gate pairs
16
, each having one P-channel transistor
18
with a drain
20
, a source
22
, and a gate
24
, and one N-channel transistor
26
with a drain
28
, a source
30
, and a gate
32
. The drain of each P-channel transistor is connected to the source of the corresponding N-channel transistor. Similarly, the source of each P-channel transistor is connected to the drain of the corresponding N-channel transistor.
The P-channel transistor will transmit a signal between the source and drain only when a negative voltage is applied to the gate with respect to the source. In contrast, the N-channel transistor will transmit a signal between the source and drain only when a positive voltage is applied to the gate with respect to the source. Thus, if opposite voltages are applied to the gates of the P-channel and N-channel transistor simultaneously, both transistors will either be switched “on” or switched “off.”
A select signal S
i
is connected to the P-channel transistor of the first transmission gate pair and the N-channel transistor of the second transmission gate pair. The select signal is also passed through an inverter
34
which produces a signal opposite the select signal. Inverter
34
may be a conventional CMOS transistor pair connected between VDD and Ground, as is described in more detail below. The inverted select signal is connected to the N-channel transistor of the first transmission gate pair and the P-channel transistor of the second transmission gate pair. As a result, when S
i
is low (also referred to herein as “Ground” or “logical 0”) the input signal I
i
connected to the first transmission gate pair is transmitted to the output node
36
of the TGM. Conversely, when S
i
is high (also referred to herein as “VDD” or “logical 1”) the input signal I
i+1
connected to the second transmission gate pair is transmitted to output node
36
.
The transmitted signal at output node
36
is connected to an output driver
11
. Similar to inverter
34
, the exemplary output driver shown in
FIG. 2
is in the form of a CMOS inverter having one P-channel transistor
38
and one N-channel transistor
40
. The P-channel transistor is connected between VDD and the N-channel transistor, while the N-channel transistor is connected between Ground and the P-channel transistor. The output node of the TGM is connected to the gates of transistors
38
and
40
. The inverter output node
42
produces a signal Q opposite the transmitted signal. Transistors
38
and
40
are appropriately sized to drive the expected output load. As can be seen from
FIG. 2
, the combination of the final TGM and output driver uses eight transistors. If desired, the output driver may include two inverters connected in series to produce the transmitted signal without inversion.
In addition to the exemplary multiplexer described above, there are many other multiplexer configurations well known in the art. For example an N:1 multiplexer can be formed by arranging a plurality of TGM's in a tree-type hierarchical structure as is known in the art. As another example, multiplexers can be formed using traditional logic gates instead of transmission gates. In view of the wide-spread use of multiplexers to implement digital logic functions, an increase in multiplexer performance or a reduction in the number of transistors needed to form a multiplexer would constitute a substantial improvement over existing technology.
SUMMARY
The invention includes a digital electronic circuit for use in implementing digital logic functions. The invented circuit has first and second sections. The first section is adapted to transmit one of N input signals, and in some embodiments is a configuration of serial cascaded TGMs. The second section is adapted to receive the signal transmitted by the first section and one or more control signals. Additionally, the second section is configured to output either an inverse of the signal transmitted by the first section or a constant logic value in response to the one or more control signals. For example, in one embodiment the second section is adapted to output either an inverse of the signal transmitted by the first section or a logical 0. In another embodiment, the second section is adapted to output either an inverse of the signal transmitted by the first section or a logical 1. The second section also may be selectively configurable in either of these configurations. In one exemplary embodiment, the second section includes no more than six CMOS transistors. In another exemplary embodiment, the second section includes no more than four CMOS transistors.
REFERENCES:
patent: 3100294 (1963-08-01), Dryden
patent: 4541067 (1985-09-01), Whitaker
patent: 4593390 (1986-06-01), Hildebrand et al.
patent: 4620117 (1986-10-01), Fang
patent: 4910417 (1990-03-01), El Gamal et al.
patent: 4926423 (1990-05-01), Zukowski
patent: 5015881 (1991-05-01), Chappell et al.
patent: 5040139 (1991-08-01), Tran
patent: 5162666 (1992-11-01), Tran
patent: 5200907 (1993-04-01), Tran
patent: 5430393 (1995-07-01), Shankar et al.
patent: 5440245 (1995-08-01), Galbraith et al.
patent: 5491431 (1996-02-01), Nasserbakht
patent: 5548552 (1996-08-01), Madurawe
patent: 5587666 (1996-12-01), Burchfield
patent: 5646558 (1997-07-01), Jamshidi
patent: 5773995 (1998-06-01), Crocker
pate
Acuff Mark W.
Tran Dzung Joseph
Callahan Timothy P.
Kolisch & Hartwell, P.C.
Nguyen Hai L.
LandOfFree
Digital electronic circuit for use in implementing digital... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Digital electronic circuit for use in implementing digital..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital electronic circuit for use in implementing digital... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2990408