Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Slope control of leading or trailing edge of rectangular or...
Reexamination Certificate
2000-10-10
2002-04-23
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Slope control of leading or trailing edge of rectangular or...
C327S112000, C327S287000
Reexamination Certificate
active
06377095
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and apparatus for controlling the rise time and fall time of a differential output digital signal. More specifically, the present invention provides for a method and apparatus to reshape a data input based upon a clock signal, provide n parallel connected output drivers, provide n sets of control signals to control the edge-rate of the n output drivers, and the output drivers provide minimum over-shoot, low jitter, low signal skew, and a well controlled rise and fall time over varied common mode voltages.
BACKGROUND OF THE INVENTION
Low Voltage Differential Signaling (hereinafter referred to as LVDS) is a technology used in data transmission systems. A low voltage differential signal produced by a line driver typically has peak-to-peak amplitudes in the range from 250 mV to 450 mV. The low voltage swing minimizes power dissipation, while maintaining high transmission speeds. Typical transmission speeds are over 100 Mbps (Mega-bits per second).
In some applications it is necessary for a line driver to produce a differential output that has a rise and fall time within specified limits. Very fast rise and fall times tend to cause a power supply line bounce condition, where the sudden increase in current driven into the power supply line causes a glitch to appear on the power supply line. Also, very fast rise and fall times may result in a glitch in the differential output signal. Glitches that appear in the power supply lines and the differential output signals can be limited by increasing the rise and fall times accordingly.
One technique used to increase the transition time (rise and fall) for a differential line driver was to increase its gate input transition time, which resulted in reducing the driver's effective data rate and increasing noise jitter due to the slower transition time. Also, the output waveforms tend to distort when the common mode voltage increases (i.e. the common mode voltage is increased from 0.8V to 2.5V) due to the non-linearity of the small-signal trans-conductance from the gate to the channel (g
m
) of the output transistors of the differential line driver. Additionally, over the common mode voltage range, the output signal of the differential line driver can have undesirable over-shoot and under-shoot causing distortion in the output signal (common mode induced jitter).
SUMMARY OF THE INVENTION
In accordance with the invention, the above and other problems are solved by an apparatus and method for generating a differential output signal. Briefly stated, the present invention relates to differential output driver circuits that produce a differential output signal in response to an input data signal. The differential output driver circuit provides for a controlled edge rate in the differential output signal when the input data signal changes logic states. Control signals are generated using an adjustable delay circuit, each subsequent control signal being delayed in time from the preceding control signal by a unit delay time. The control signals control N output drivers, each of the N output drivers having an output signal coupled to the differential output signal. Each of the N output drivers contributes a portion of the differential output signal. When the input data signal changes from one logic state to another, the differential output signal will have a defined edge rate determined by the unit delay time, N, and the contributing portion from each of the N output drivers. In one example, the unit delay time is determined by a delay time through a buffer that has a controlled current limit. The controlled current limit is provided by a current source that is compensated for semiconductor processing variations and temperature variations. Variations in semiconductor processing are corrected by producing a current that is inversely proportional to the trans-conductance of a MOS transistor reference device. Since the current limit in the buffer is raised for slower transistors (lower trans-conductance), the unit delay time is maintained within tolerable limits when the process parameters vary. The differential output driver circuit is compensated to provide minimum over-shoot, low jitter, low distortion, low signal skew, and a controlled rise and fall times over varied common mode voltages.
In accordance with an aspect of the invention, a differential output signal is produced in response to an input data signal. A control logic circuit produces control signals corresponding to the input data, and a driver circuit produces the differential output signal in response to the control signals. The driver circuit has N driver cells, each of the N driver cells generating a respective output signal in response to a respective control signal. The respective output signals of the N driver cells are arranged such that each of the N driver cells provides a portion of the differential output signal.
In accordance with a further aspect of the invention, a change in the input data signal results in a change in the control signals for one of the N driver cells at a time different from the other of the N driver cells such that the rise time of the differential output signal is proportional to the time difference.
In accordance with yet a further aspect of the invention, a change in the input data signal results in a change in the control signals for one of the N driver cells at a time different from the other of the N driver cells such that the fall time of the differential output signal is proportional to the time difference.
In accordance with another feature of the invention, a control logic circuit has N delay circuits, each of the N delay circuits including: a delay cell having an input and output, the delay cell is current limited by a current limit amount, a delay time corresponds to the delay between an input change and an output change, and the delay time is proportional to the current limit amount.
In accordance with yet another feature of the invention, the control logic circuit includes a delay circuit with an input and output, a delay time from the input to the output is controlled by a current reference, and the current reference is compensated to reduce variations in the delay time. In one embodiment of the invention, the current reference includes a MOS transistor that has a trans-conductance parameter, the MOS transistor is arranged to conduct a current that is proportional to the trans-conductance parameter, a difference circuit provides another current that corresponds to a difference between a temperature compensated current and the current, and a reference MOS transistor is arranged to conduct a bias current that corresponds to a sum of the another temperature compensated current and the another current such that the bias current is inversely proportional to the trans-conductance and variations in the delay time due to changes in trans-conductance are reduced. In another embodiment of the invention, the current reference includes a resistor having a resistor value and a temperature coefficient, a temperature compensated current is coupled to the resistor to produce a gate voltage that is independent of temperature, a MOS transistor is arranged to conduct a current that is proportional to the gate voltage, a difference circuit provides another current that corresponds to a difference between another temperature compensated current and the current, and a reference MOS transistor is arranged to conduct a bias current that corresponds to a sum of the another temperature compensated current and the another current, such that the bias current is independent of temperature and variations in the delay time due to changes in temperature are reduced.
According to a feature of the invention, a differential output signal is produced in response to an input data signal. The driver circuit has N driver cells, each of the N driver cells generating a respective output signal in response to a respective control signal. A current source provides a controlled current. The controlled current is coup
Callahan Timothy P.
Hertzberg Brett A.
Luu An T.
Merchant & Gould P.C.
National Semiconductor Corporation
LandOfFree
Digital-edge-rate control LVDS driver does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Digital-edge-rate control LVDS driver, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital-edge-rate control LVDS driver will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2829446