Digital dynamic trace adjustment pulse width modulate...

Details Digital dynamic trace adjustment pulse width modulate... Digital dynamic trace adjustment pulse width modulate...

2003-04-16

2004-11-02

Han, Jessica (Department: 2838)

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

C323S322000, C375S238000

Reexamination Certificate

active

06812681

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a digital dynamic trace adjustment pulse width modulate controller comprising: a comparator unit and a converter unit, wherein the comparator unit outputs/inputs a voltage (Vo) and a reference voltage (Vref), and also outputs a phase signal having low-level and high-level standards and further a core digital processing unit being also included, wherein the core digital processing unit outputs a pulse width modulate signal.
Through the function of the previously mentioned units, the feature of the invention is mainly to use a digital dynamic trace adjustment pulse width modulate controller to suit for voltage variation, and to use the core processing unit to receive pulse width modulate phase signal. It is observed that when the output voltage is gradually dropping or rising, changing the pulse width modulate phase signal on the output end, the duty rate of the phase signal will be maintained at a fifty percent degree.
Through the function of the previously mentioned units, the root mean square of the output voltage of the converter unit is equal to the root mean square of the reference voltage.
BACKGROUND OF THE INVENTION
U.S. Pat. No. 5,629,610 discloses a wholly digital electric current model pulse width modulate controller comprising two comparators combined together. Each of the comparators reads in the voltage drop of a sensor resistance. The first comparator utilizes an open loop electric current model control and the second comparator builds a higher second electric current threshold, wherein the electric current threshold is higher than the first electric current threshold. When the electric current is output, the current level standard runs free across the second current threshold and the second comparator triggers a disabling circuit of an output power transistor and sustains for a fixed period of time.
The situation may occur, because,e in off-phase state, the output power transistor, the additional stored electric energy is insufficiently discharging electricity from load circuitry inductance. And the frequency can be kept out of the intentional frequency range to avoid interference.
U.S. Pat. No. 6,373,334 B1 pertains to a device for reducing the distortion and noise of a high power digital pulse width modulate amplifier. Through measuring of the difference between the estimated output signal and the real output signal, an analog error is generated due to analog to digital convert (adc) process error. The digital error signal is then added to real time delta sigma modulator correction process. Preferably, not only the modulate signal can he adjusted by a feedback process, but also the well known electric circuitry predicted error can be adjusted through time signal delta sigma modulator.
A certain analog-digital converter allows this loop delay to be reduced to minimum and not to sacrifice its precision.
SUMMARY OF THE INVENTION
A first object of the present invention is to use a core processing unit to receive the output pulse width modulate phase signal. Upon sensing rising or dropping of an output voltage, changing the pulse width modulate signal of the output end such that the time elapses of high level standard and low level standard arc equal. That is, the duty rate of signal phase is maintained at fifty percent degree.
A second object of the present invention is to use a core processing unit to receive the pulse width modulate phase signal. Upon sensing rising or dropping of an output voltage, changing the pulse width modulate signal of the output end such that the root mean square of the phase signal output voltage of the converter unit is equal to the root mean square of the reference voltage.
A third object of the present is to proceed a digital dynamic trace adjustment such that the process of analog to digital converter is avoided, wherein the adjustment uses a comparator unit to output a voltage standard that lies within (but not included) the maximum voltage level standard and the minimum voltage level standard of a reference voltage (Vref) and proceed the digital dynamic trace pulse width modulate adjustment process.
The present invention will become more obvious from the following description when taken in connection with the accompanying drawings that show, for purpose of illustration only, preferred embodiments in accordance with the present invention.


REFERENCES:
patent: 5629610 (1997-05-01), Pedrazzini et al.
patent: 6169669 (2001-01-01), Choudhury
patent: 6373334 (2002-04-01), Melanson

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