Digital duty cycle correction loop apparatus and method

Details Digital duty cycle correction loop apparatus and method Digital duty cycle correction loop apparatus and method

1998-09-14

2000-03-21

Wells, Kenneth B.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Rectangular or pulse waveform width control

327172, 327261, H03K 3017

Patent

active

060407263

ABSTRACT:
An apparatus for providing a clock signal having a fifty-percent duty cycle that comprises a signal input having a plurality of pulses. A delay means is provided for producing a delayed output signal having a plurality of delayed pulses, each of the plurality of delayed pulses being delayed relative to one of the plurality of pulses. A means for measuring a first delay between one of said plurality of delayed pulses and a next of the plurality of pulses is provided. A means for measuring a second delay between one of the plurality of pulses and a corresponding delayed pulse of the plurality of delayed pulses is provided. A means for comparing the first delay to the second delay is provided. A means for increasing the delay of the delay means if the first delay is greater than the second delay and decreasing the delay of the delay means if said first delay is less than the second delay is provided. A means for combining the signal input and the delayed output signal thereby outputting the clock signal having a fifty-percent duty cycle is provided.

REFERENCES:
patent: 4799022 (1989-01-01), Skierszkan
patent: 5245637 (1993-09-01), Gersbach et al.
patent: 5260608 (1993-11-01), Marbot
patent: 5481228 (1996-01-01), Badyal

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