Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2000-07-27
2004-06-08
Liang, Regina (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S087000, C345S090000, C345S092000, C345S094000, C345S095000, C345S098000, C345S099000, C345S100000, C345S204000, C345S213000
Reexamination Certificate
active
06747625
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a digital driving circuit for a liquid crystal display (LCD), and more particularly to a digital driving circuit having an improved construction with such a reduced width as to be applicable to a high-density LCD.
2. Description of the Prior Art
With the development of multimedia systems, the amount of information being used therein has recently increased at the ratio of a geometric progression and it has also been accelerated to make the resolution and density of a display higher to display the increased amount of information. In particular, in order to act up to a high densification of an LCD that is a representative runner in a flat display field, making the density of a panel of the LCD higher is in progress.
In an LCD using polysilicon thin-film transistors, a peripheral driving circuit must occupy a smaller area on a panel to increase the size of a screen. To this end, researches have been conducted in reducing a width or the LCD panel occupied by the driving circuit. One approach is to reduce a line width of the driving circuit.
However, a fabrication process for reducing the line width of the driving circuit is so complicated as to cause various problems such as an increase in inferiority rate, a degradation in productivity, etc. Further, it is inevitable to make a large-scale facility investment to perform the complicated fabrication process.
As a result, there has been required a method for structurally reducing the width of the driving circuit by modifying a method of driving the polysilicon thin-film transistors contained in the LCD.
FIG. 1
is a circuit diagram showing a part of a conventional digital driving circuit which receives all bits of digital video information at a time and drives an LCD, wherein the digital video information is of eight bits.
In
FIG. 1
, the reference numeral
10
denotes first transfer switches for transferring external input digital video information to a (j−1)th column,
11
denotes second transfer switches for transferring the external input digital video information to a jth column, and
12
denotes third transfer switches for transferring the external input digital video information to a (j+1)th column.
Also, the reference numeral
13
denotes a data bus for loading the external input digital video information thereon,
14
denotes a line of the data bus
13
corresponding to an eighth bit or most significant bit (MSB) of the 8-bit digital video information, and
15
denotes a line of the data bus
13
corresponding to a first bit or least significant bit (LSB) of the 8-bit digital video information.
Also, the reference numeral
16
denotes digital latches for temporarily storing the digital video information transferred by the first to third transfer switches
10
-
12
,
17
denotes a first digital bus for transferring the digital video information stored in the digital latches
16
to the (j−1)th column,
18
denotes a second digital bus for transferring the digital video information stored in the digital latches
16
to the jth column, and
19
denotes a third digital bus for transferring the digital video information stored in the digital latches
16
to the (j+1)th column.
The data bus
13
is composed of eight lines from the LSB data bus line
15
up to the MSB data bus line
14
, which extend in a row direction (i.e., a vertical direction to the column direction).
The operation of the conventional digital driving circuit with the above-mentioned construction will hereinafter be described.
First, when jth digital video information is loaded on the data bus
13
, the second transfer switches
11
are turned on to transfer it to the jth column. At this time, the digital video information is stored in the data latches
16
through the turned-on second transfer switches
11
. Then, the digital video information stored in the data latches
16
is transferred to a digital/analog converter (not shown) through the second digital bus
18
of the jth column so that it can be converted into an analog signal.
However, the conventional digital driving circuit for the LCD requires eight data bus lines and a large number of data latches arranged in the row direction as shown in
FIG. 1
to drive one column for the process of 8-bit digital video information. As a result, the data bus and inverters used as the data latches occupy a large area on a panel of the LCD.
In other words, because of the simultaneous process of all bit information, the conventional digital driving circuit for the LCD requires the same number of data bus lines as that of bits to be processed and the associated number of data latches for data storage arranged vertically to the column direction to drive one column, resulting in an increase in the area on the LCD panel occupied by inverters used as the data latches. This makes it difficult to integrate the digital driving circuit on the LCD panel with a narrow width and thus to make the LCD higher in density.
SUMMARY OF THE INVENTION
Therefore, the present invention has been made in view of the above problems, and it is an object of the present invention to provide a digital driving circuit for a liquid crystal display which is capable of sequentially processing bit information of digital video information to reduce the number of data bus lines and data latches used therein.
In accordance with the present invention, the above and other objects can be accomplished by a provision of a digital driving circuit for a liquid crystal display which sequentially receives and displays n-bit digital video information from a data bus on a bit basis, comprising a first data latch for sequentially storing the digital video information from the data bus on a bit basis; a shift register for synchronizing a latching operation of the first data latch with bit positions of the digital video information from the data bus; a second data latch for storing the digital video information stored in the first data latch temporarily before digital/analog conversion; and a digital/analog converter for sequentially converting the digital video information stored in the second data latch into analog signals on a bit basis.
Preferably, the digital driving circuit further comprises an analog buffer connected between the digital/analog converter and a data line, the analog buffer being enabled when the data line has a large parasitic capacity.
Further, preferably, the data bus is composed of a single line and the first data latch receives and stores digital video information of one column from the data bus line. Alternatively, the data bus may be composed of first and second lines and the first data latch may receive and store digital video information of one column from the first data bus line and an inverted version of the digital video signal of the column from the second data bus line.
Further, preferably, the digital/analog converter includes first and second electrostatic capacitors connected in parallel to each other and having the same electrostatic capacity, the first and second electrostatic capacitors cooperating to output a charged voltage value as an analog signal; a charging switch connected to a first reference voltage source for charging the first and second electrostatic capacitors when bit information of the digital video information from the second data latch is 1 in logic; a discharging switch connected to a second reference voltage source for discharging the first and second electrostatic capacitors when the bit information of the digital video information from the second data latch is 0 in logic; a redistribution switch connected between the first and second electrostatic capacitors for redistributing charges stored thereon; and an initialization switch for initializing voltages across the first and second electrostatic capacitors.
REFERENCES:
patent: 5576737 (1996-11-01), Isozaki
patent: 5856816 (1999-01-01), Youn
patent: 5956010 (1999-09-01), Asao et al.
patent: 6008801 (1999-12-01), Jeong
patent: 6014122 (200
Chung Hoon-Ju
Han Chul-Hi
Lee Seung-Woo
Bachman & LaPointe P.C.
Korea Advanced Institute of Science and Technology
Nguyen Jennifer T.
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