Computer graphics processing and selective visual display system – Display driving control circuitry
Reexamination Certificate
2001-03-15
2004-10-05
Shankar, Vijay (Department: 2673)
Computer graphics processing and selective visual display system
Display driving control circuitry
C345S004000, C345S005000, C345S006000
Reexamination Certificate
active
06801193
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an image display apparatus, and more specifically to a digital drive apparatus to drive a light emission apparatus.
2. Description of the Related Art
Image display apparatuses have various types in terms of multi-color image reproduction. The first type is a three panel type applied for projectors. This method uses, for example, three liquid crystal panels corresponding to three color light components of red, green, and blue, and combines three color images produced by the three liquid crystal panels, so as to reproduce a multi-color image. The second type is a color filter type applied for direct viewing image display apparatuses. This method uses, for example, one liquid crystal panel, where three light modulation elements (liquid crystal cells) emitting different colors form one pixel, and reproduces a multi-color image by means of spatial color mixing. The third type is a color sequential type. This method, for example, successively irradiates one liquid crystal panel with three color light components and sequentially displays corresponding color images produced by the liquid crystal panel. Namely this method reproduces a multi-color image by means of the time-based color mixing function of human eyes.
The image display apparatus generally includes a light modulation device, such as a liquid crystal panel, and a digital drive device that drives the light modulation device. The digital drive device has a memory cell array including a plurality of memory cells that respectively actuate a plurality of light modulation elements included in the light modulation device.
In the course of using the image display apparatus, for example, at the time of rewriting an image, each light modulation element should forcibly be set to a predetermined state such as OFF state (state that prohibits emission of light). Especially in the image display apparatus that adopts the color sequential technique, the digital drive device is required to actuate the light modulation device in response to color image data corresponding to each of color light components successively output to the light modulation device. The digital drive device should thus set each light modulation element in OFF state before the light modulation device is irradiated with each color light component.
The prior art digital drive device, however, has difficulties in setting the light modulation element in OFF state. The prior art system uses two sub-frame periods for display of a color image of one picture screen. This takes a relatively long time. In the prior art technique, each light modulation element is selectively set in ON state (state that allows emission of light) in a fist sub-frame period, and is necessarily set in OFF state in a second sub-frame period. Color image data are written into each memory cell of the digital drive device in the first sub-frame period. Specific data to set each light modulation element in OFF state are then written into the memory cell in the second sub-frame period.
The problem discussed above is not restricted to the image display apparatus that adopts the color sequential technique but is also found in image display apparatuses that adopt different techniques.
SUMMARY OF THE INVENTION
The object of the present invention is to solve the above problem of the prior art systems and thus to provide a technique that enables each light emission element, such as a light modulation element, included in an image display apparatus to be readily set in a predetermined state.
At least part of the above and the other related objects is attained by a first apparatus of the present invention that is a digital drive apparatus, which has a memory cell array including a plurality of memory cells that are arranged in a matrix. Each of the memory cells includes: a storage section that stores a supply of data therein and that is capable of keeping output corresponding to the stored data; a transfer element that is capable of transferring the data to the storage section; an address terminal that supplies an address signal to the transfer element, the address signal controlling operation of the transfer element; a data terminal that is connected with the transfer element and supplies the data to the storage section via the transfer element; an output terminal that outputs the data stored in the storage section; and a reset terminal that supplies a reset signal to the storage section, the reset signal setting the output of the storage section to a predetermined state regardless of the data previously stored in the storage section.
In this digital drive apparatus, each memory cell has a reset terminal. This arrangement enables the output of the storage section to be readily set to a predetermined state, irrespective of the data previously stored in the storage section. Application of this digital drive apparatus to an image display apparatus having a light emission apparatus enables each light emission element to be readily set in a predetermined state.
In accordance with one preferable embodiment of the above digital drive apparatus, the storage section includes an inverter and either a 2-input NAND gate or a 2-input NOR gate. An output terminal of the 2-input NAND gate or the 2-input NOR gate is connected with an input terminal of the inverter. One input terminal of the 2-input NAND gate or the 2-input NOR gate is connected with an output terminal of the inverter, whereas the other input terminal is connected with the reset terminal.
This arrangement simplifies the construction of the storage section.
In the digital drive apparatus, it is preferable that the memory cell further includes a buffer circuit that converts an output voltage of the storage section.
This arrangement enables each memory cell to have an output of an arbitrary voltage level, while desirably reducing the power consumption of the storage section. Application of this digital drive apparatus to an image display apparatus having a light emission apparatus allows actuation of each light emission element that works at an arbitrary voltage level.
In accordance with another preferable embodiment of the above digital drive apparatus, the memory cell array further includes: a plurality of first signal lines, each of the first signal lines connecting in parallel one set of address terminals, which are included in one set of memory cells aligned in a direction of rows; a plurality of second signal lines, each of the second signal lines connecting in parallel one set of data terminals, which are included in one set of memory cells aligned in a direction of columns; and a plurality of third signal lines, each of the third signal lines connecting in parallel one set of reset terminals, which are included in the one set of memory cells aligned in the direction of rows. In this embodiment, the digital drive apparatus further has: a first driver circuit that sequentially supplies the address signal to each set of memory cells aligned in the direction of rows via the plurality of first signal lines; a second driver circuit that simultaneously supplies the data signal to respective sets of memory cells arranged in the direction of columns via the plurality of second signal lines; and a third driver circuit that sequentially supplies the reset signal to each set of memory cells aligned in the direction of rows via the plurality of third signal lines.
This arrangement sequentially sets the outputs of the respective sets of memory cells arranged in the direction of rows to a predetermined state.
In the digital drive apparatus of the above embodiment, it is preferable that the third driver circuit is capable of supplying the reset signal to a specific set of memory cells at a specific timing after the first driver circuit has supplied the address signal to the specific set of memory cells.
This arrangement causes the output of the storage section to be set to a predetermined state at a specific timing after the data are written into the storage section. Application of this di
Nakamura Jun-ichi
Seki Hideya
Yonekubo Masatoshi
Dharia Prabodh M.
Oliff & Berridg,e PLC
Seiko Epson Corporation
Shankar Vijay
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