Digital division circuit using N/M-bit subtractor for N subtract

Details Digital division circuit using N/M-bit subtractor for N subtract Digital division circuit using N/M-bit subtractor for N subtract

1989-08-29

1991-06-25

Shaw, Dale M.

Boots, shoes, and leggings

G06F 752

Patent

active

050273094

ABSTRACT:
In a division circuit, a dividend register (7) and a remainder register (14) are connected so that a bit in the MSB of the former is shifted to the LSB of the latter. Higher bits of an N-bit divisor are monitored by a detector (18) and a zero-detect (ZD) signal is generated when they are all "0"s. In the presence of the ZD signal, subtraction is performed by an N/2-bit subtractor (28) between lower-bit data of a divisor and data in the remainder register and, in the absence of the ZD signal, first subtraction is performed between lower-bit data of the divisor and higher-bit data of the dividend register (7) and second subtraction is performed between higher-bit data of the divisor register and data in the remainder register (14). A "1" is written into the LSB of the dividend register (7) either in response to a "1" in the MSB of the remainder register (14) or when no borrow results from subtractions. In the presence of the ZD signal, the result of each subtraction is stored in a first latch, the remainder and dividend registers are one-bit shifted and the remainder register (14) is loaded with the stored data when a "1" is stored into the LSB of the dividend register. In the absence of the ZD signal, the results of subtraction are respectively stored in first and second latches (12;71,8;72), and the registers (14,7) are shifted and loaded with the stored data when a "1" is stored into the LSB of the dividend register (7). A quotient and a remainder are derived from the dividend and remainder registers after subtraction is repeated N times.

REFERENCES:
patent: 4414692 (1983-11-01), Grube
patent: 4692891 (1987-09-01), Yamaoka et al.
patent: 4817048 (1989-03-01), Rawlinson et al.
Sanyal, "An Algorithm for Nonrestoring Division", Computer Design, May 1977, pp. 124-127.

Affiliated with

Also associated with

Rating

Digital division circuit using N/M-bit subtractor for N subtract does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Digital division circuit using N/M-bit subtractor for N subtract, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital division circuit using N/M-bit subtractor for N subtract will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1045619