Digital diversity receiver, comprising an APC loop for locking i

Details Digital diversity receiver, comprising an APC loop for locking i Digital diversity receiver, comprising an APC loop for locking i

1979-12-19

1981-05-26

Safourek, Benedict V.

Pulse or digital communications

Spread spectrum

Direct sequence

455132, H04B 708

Patent

active

042702100

ABSTRACT:
A digital signal combining circuit for a diversity receiver for digital communication comprises buffer memories (16) for memorizing digital signal sequences produced by receiver units (11, 12), respectively, and an APC loop (26-39) for locking the phases of read-out clocks for simultaneously reading the memories to an averaged phase of the digital signal sequences. No code error appears in an output signal of the receiver provided that the phase difference between two of the digital signal sequences from which the output signal is selected, is less than m bit periods, where m represents the number of memory cells of each buffer memory.

REFERENCES:
patent: 3555427 (1968-02-01), Hatton
patent: 3975687 (1976-08-01), Tan
patent: 4015205 (1977-03-01), Ikeda
patent: 4035728 (1977-07-01), Ishikawa
patent: 4143321 (1979-03-01), Norsworthy

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