Coded data generation or conversion – Phase or time of phase change
Reexamination Certificate
1999-07-07
2002-11-19
JeanPierre, Peguy (Department: 2819)
Coded data generation or conversion
Phase or time of phase change
C345S213000
Reexamination Certificate
active
06483447
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to digital display units for use in computer systems, and more specifically to a method and apparatus which dynamically adjusting the sampling phase while sampling an analog display signal to recover the encoded digital data.
2. Related Art
Digital display units (e.g., flat panel monitors) are often used in computer systems for displaying images encoded in analog display signals. In a typical situation, a graphics source (typically including a digital to analog converter) generates an analog display signal from pixel data representing an image frame according to well known standards such as VGA or SVGA.
An analog display signal generally contains display data signal and associated synchronization signals. The display data signal may be viewed as a series of successive portions in time domain, with each portion being generated from a pixel data element representing a point of an image. The image portions are typically generated under the control of a source clock, which drives a digital to analog converter (DAC). The DAC generates the analog display data according to the source clock signal.
The manner in which a digital display unit displays images and some problems with such display are described below.
A digital display unit generally recovers the pixel data elements which are encoded in the display data signal of a received analog display signal. The recovery process usually entails generating a sampling clock from the synchronization signals (contained in the analog display signal), and sampling the analog display data according to the sampling clock. Pixel data elements representing an image are generated from such sampling.
In general, the pixel data elements resulting from the sampling need to (at least substantially) equal the pixel data elements from which display data portion of a received analog signal is generated so that the images represented by both sets of pixel data elements are the same. One of the requirements to achieve such equality is that the sampling clock be generated with appropriate phase and frequency such that each pixel data element is recovered as accurately as possible.
At least in some environments such as those based on VGA and SVGA, several challenges may be presented in generating a sampling clock with the appropriate phase and frequency as the synchronization signals accompanying display signals do not contain clocking information for each pixel data element. Instead, a horizontal synchronization signal is typically provided, which generally indicates the transition to a next horizontal line.
Clock recovery circuits (such as phase lock loops) have been implemented to generate sampling clock signals based on the transitions indicated by horizontal synchronization signals. Usually, the phase of the (divided) sampling clock is compared with the horizontal synchronization signals for every line, and the sampling clock is adjusted based on the comparison. The phase of the horizontal synchronization signals typically represents the average phase of the source clock for an entire line.
The phase adjustment of a sampling clock based on infrequent comparisons may not be acceptable in several situations. For example, in the VGA and SVGA environments of above, the source clock may generate non-uniformly spaced (in time domain) pulses due to factors such as phase jitter and frequency drift resulting from, for example, imperfect hardware used in generating the source clock. The non-uniformity in the source clock may not be tracked accurately by the sampling clock.
The absence of proper tracking may result in inaccurate recovery of the pixel data elements encoded in a received analog display signal, particularly when the analog signals are encoded with high resolution images at a high refresh rate. As may be readily appreciated, the pixel processing period (the time duration for encoding a pixel data element in a display signal) is generally short under such circumstances, and there may be a narrow window (in time domain) in which to sample each display data portion representing a pixel data element.
The window is typically narrow because of the limited bandwidth practically present between a graphics source and a digital display unit and the short pixel processing period. If a display data portion representing a pixel is not sampled in the corresponding window, the pixel data element may not be recovered accurately.
The absence of proper tracking typically affects the display quality. For example, display artifacts may be observed on a display screen. The artifacts are generally more visible towards the right end of the screen. In some instances, the artifacts manifest as vertical bars on the displayed images. The artifacts are of particular concern when a graphics source uses imprecise components (e.g., analog PLLs operating in high noise environments) for generating a source clock signal.
To avoid such artifacts and to facilitate accurate recovery of pixel data elements, users of display units are often required to adjust the sampling phase. Typically, an on-screen-display menu is provided to facilitate a user manual adjustment. However, such manual techniques are often cumbersome even for the knowledgeable users, and are thus undesirable.
Therefore, what is needed is a method and apparatus for dynamically adjusting the phase of the sampling clock such that the pixel data elements can be recovered accurately and display artifacts can be avoided.
SUMMARY OF THE INVENTION
The present invention is directed to a digital display unit which displays the images encoded in an analog display signal received from a graphics source. The analog display signal may contain display data signal and associated synchronization signals. Each portion of the display data signal may be generated from a pixel data element. Many such pixel data elements may represent an image frame.
The synchronization signals do not contain the clock for recovering each of the pixel data elements, and accordingly a sampling clock enabling such recovery is generated in the digital display unit in accordance with the present invention. The manner in which the sampling clock is generated in some example embodiments is described below in further detail.
A digital display unit in accordance with the present invention examines the display data signal to determine the deviation in phase of a source clock signal from a sampling clock signal. The phase of the sampling clock is modified to closely track the source clock signal. As the sampling clock tracks the source clock closely, the pixel data elements encoded in the display data signal may be recovered accurately.
In an embodiment, the deviations in phase are determined by examining the display data signal for the boundary of display data portions representing two successive pixel data elements. As the boundaries generally provide the timing information of the source clock signal, the phase of the source clock signal may be compared with that of the sampling clock signal.
In addition, the examined portion (or length) of the display data signal may be minimized by first determining an expected boundary. The expected boundary may be determined based on the synchronization signal accompanying the display data signal. Thus, an aperture covering a small area around the expected boundary can be examined to determined an accurate boundary.
The time difference of the expected boundary and accurate boundary represents the deviation of phase of the sampling clock signal from that of the source clock signal. Thus, the time difference can be used to adjust the phase of the sampling clock signal. In an embodiment, the time difference is passed through a filter to minimize unneeded short term fluctuations.
According an another aspect of the present invention, the expected boundary is determined by taking a few analog timing samples in the aperture. Successive timing samples are compared to determine the actual boundary. In general, transitions in voltage levels (such as a sing
Genesis Microchip (Delaware) Inc.
Jean-Pierre Peguy
Staas & Halsey
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