Digital differential phase-shift keyed decoder

Details Digital differential phase-shift keyed decoder Digital differential phase-shift keyed decoder

1988-11-17

1990-10-23

Safourek, Benedict V.

Pulse or digital communications

Repeaters

Testing

375 84, 329304, H03D 322

Patent

active

049658107

ABSTRACT:
Digital circuits increase reliability of a decoder for differential phase-shift keyed signals. A tapped delay line delays the input signal by a variable amount, substantially equal to one bit time of the modulated data, and provides the delayed signal to a multiplier for generating a product signal. In response to changes in frequency of the input signal, a control system selects different taps of the delay line to provide the delayed signal for multiplication by the modulated input signal. The control signal includes a feedback loop, wherein a phase difference between the signal at the selected tap and the input signal is used to change a count in an up/down counter. A tap selecting multiplexer provides an output from specified taps in response to particular values of the count.

REFERENCES:
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patent: 4229824 (1980-10-01), En
patent: 4379266 (1983-04-01), Rubin
patent: 4746872 (1988-05-01), Yamagata et al.
patent: 4769816 (1988-09-01), Hochstadt et al.
patent: 4807251 (1989-02-01), Shibano
Digital Analog and Data Communication, pp. 420-421, William Sinnema, Reston Publishing Co., Reston, Va., 1982.
Analog Digital Communications, pp. 160-162, W. David Gregg, John Wiley & Sons, N.Y., Santa Barbard, London, 1977.

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