Pulse or digital communications – Synchronizers
Reexamination Certificate
1998-02-02
2001-07-31
Pham, Chi (Department: 2631)
Pulse or digital communications
Synchronizers
C375S355000, C370S503000, C327S040000
Reexamination Certificate
active
06269136
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and apparatus for the synchronization of data between two distinct clock domains.
BACKGROUND OF THE INVENTION
In numerous systems capable of the transmission and the reception of data, there is often a need for the synchronization of data transmitted with an associated clock signal having known frequency and varying phase, with the clock signal of the receiving system. For example, such synchronization is necessary in a master system which transmits a request data stream with an associated request clock signal to a subsidiary system which receives the data stream and request clock signal and transmits a response data stream, with an associated response clock signal. The master system receives the response data steam and associated response clock signal. The response clock signal has a known frequency, but unknown phase, due to a variable delay in the data and clock paths.
The variable delay occurs in both the request data stream and request clock signal and the response data stream and response clock signal due to the combination of circuit delays and wire transmission delays. The delay may also vary after the system is initialized, due to the dependence of the delays upon, for example, temperature, operating voltage, and physical tension of the cable connecting the systems. In both cases (i.e., transmission and reception), the received clock signal can be used to generate a sampling clock which is used to reliably sample the data. The subsidiary system may use the sampling clock to synchronously clock all its storage elements or delay elements (such as latches, flip-flops, and phase delays), thus avoiding any problem of clock asynchrony.
However, the master system is faced with a Hobson's choice, as the master system may choose synchrony with either the request clock signal or the response clock signal, but not both. If synchrony with the request clock signal is maintained, a data synchronizer must be placed in the receiver of the master system, as the phase of the response clock signal is not predictable with respect to the request clock signal.
The choice of an optimal main system clock rate may depend on factors other than the required communication rate between the main and subsidiary systems, such as the delay of internal circuits and interconnections, required internal computation rates, and so on. When the rate of the main system clock is different from the rate of the request clock signal, both the request clock signal and response clock signal are asynchronous with the main system clock, and data synchronization is required in data paths both in the request data path and the response data path.
Thus, in systems transmitting and receiving data to and from various subsidiary systems, there exists a need for a method and apparatus for synchronizing both request data streams and response data streams to the clock signal of the receiving device, which accomplishes the synchronization with minimal delay and maximum reliability.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method and apparatus for synchronizing a request data signal (also referred to as a data stream) to a communications clock and to synchronize a response data signal to a main system clock, with the synchronization being accomplished with minimal delay and maximum reliability.
More specifically, the present invention relates to a method of synchronizing a data stream between two distinct clock domains. The novel method comprising the steps of receiving the data stream at a first clock rate M, sequentially loading the data stream into a plurality of registers at the first clock rate, utilizing a digital differential analyzer to generate a synchronization signal having a frequency proportional to a ratio of the first clock rate M and a second clock rate N, and sequentially reading the plurality of registers at a rate corresponding to the frequency of the synchronization signal.
The present invention also relates to an apparatus for synchronizing a data stream between two distinct clock domains. The apparatus comprises an input means for receiving the data stream at a first clock rate M, means for sequentially loading the data stream into a plurality of registers at the first clock rate, a digital differential analyzer operative for generating a synchronization signal having a frequency proportional to a ratio of the first clock rate M and a second clock rate N; and means for sequentially reading the plurality of registers at a rate corresponding to the frequency of the synchronization signal.
As described in detail below, the method and apparatus of the present invention provides important advantages over the prior art. Most importantly, the present invention performs the required data synchronization with minimal delay and maximum reliability.
The present invention accommodates large variations in phase delay of the subsidiary system, variations which may be in excess of the cycle time. Additional delay is accommodated by adjusting the number of registers into which the data stream is loaded into and read from.
The present invention avoids the use of repeated asynchronous sampling of the high bandwidth signals and clocks, which is a source of failure in prior art synchronizer designs. Asynchronous sampling is the use of an unsynchronized clock to sample a signal or clock; when the sample point occurs nearly simultaneous with the time that the signal or clock changes, an inherent metastability occurs in the sampling circuit, which can take an arbitrarily long time to be resolved into a stable logic level. After initialization, the present invention has no use of asynchronous sampling, so it is free from synchronizer failure.
The present invention allows for the use of a wide variety of clock rates in a single design, as timing-sensitive delay elements are limited to the phase-locked loops and phase-delay elements. These elements are explicitly programmable with the desired clock rates (M and N) so that necessary adjustments to these elements need not be discovered dynamically from the incoming clock signals.
Additional advantages of the present invention will become apparent to those skilled in the art from the following detailed description of exemplary embodiments of the present invention.
The invention itself, together with further objects and advantages, can be better understood by reference to the following detailed description and the accompanying drawings.
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patent: 5621775 (1997-04-01), Etienne
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patent: 5956377 (1999-09-01), Lang
Hansen Craig C.
Robinson Timothy B.
McDermott & Will & Emery
MicroUnity Systems Engineering, Inc.
Pham Chi
Tran Khai
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