Digital detector/filter for synchronizing signals

Facsimile and static presentation processing – Facsimile – Specific signal processing circuitry

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358153, H04N 508

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active

050310410

ABSTRACT:
A detector for vertical synchronizing pulses comprises a nonwrapping up/down counter and a comparator. The counter level samples a composite synchronizing signal at a sampling rate. The counter has a numerical output which increases responsive to detection of said level during a sample interval and decreases responsive to nondetection of said level during a sample interval. The comparator generates a vertical sync detection pulse when the numerical output of the counter is greater than a reference value. In order to provide hysteresis, the numerical value os alternately one of first and second numerical reference counts, the first reference count being greater than the second reference count. The comparator initiates the vertical sync detection pulse when the numerical output of the counter rises above the first reference count and terminates the vertical sync detection pulse when the numerical output of the counter falls falls below the second reference count. The numerical reference supplied to the comparator is changed at times corresponding to initiation and termination of each vertical sync detection pulse. A pulse shaping circuit may comprise a latch for sampling the output of the comparator and generating a vertical synchronizing signal.

REFERENCES:
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patent: 4166250 (1979-08-01), Meki et al.
patent: 4214270 (1980-07-01), Morito
patent: 4357630 (1982-11-01), Odaka
patent: 4600944 (1986-07-01), Williams
patent: 4684988 (1987-09-01), Johannes
patent: 4697211 (1987-09-01), Balaban et al.
patent: 4698697 (1987-10-01), Balaban et al.

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