Digital detection of blockers for wireless receiver

Coded data generation or conversion – Analog to or from digital conversion – Nonlinear

Reexamination Certificate

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Details

C341S155000

Reexamination Certificate

active

07151473

ABSTRACT:
A receiver100is provided. The receiver100comprises an in-phase analog-to-digital converter112operable to detect a saturation condition of the in-phase analog-to-digital converter112and to adjust the amplitude of a in-phase signal processed by the in-phase analog-to-digital converter112to remove the in-phase analog-to-digital converter112from the saturation condition and a in-phase digital filter114operable to adjust a gain applied to a digital input to the in-phase digital filter114from the in-phase analog-to-digital converter112, the adjustment of the gain substantially inversely proportional to the adjustment of the amplitude of the in-phase signal processed by the in-phase analog-to-digital converter112. In an embodiment, the receiver100also comprises a quadrature path that is substantially similar to the in-phase path, and the in-phase path and the quadrature path comprise a direct conversion receiver. In an embodiment, the in-phase analog-to-digital converter112and the in-phase digital filter114comprise an intermediate frequency receiver.

REFERENCES:
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patent: 6476745 (2002-11-01), Evans et al.
patent: 2004/0184562 (2004-09-01), Wang et al.
patent: 2004/0259510 (2004-12-01), Audinot et al.
patent: 2005/0070325 (2005-03-01), Bellaouar et al.
UNKNOWN; “Demystifying Sigma-Delta ADCs”; Dallas Semiconductor Maxim; http://www.maim-ic.com/appnotes.cfm/appnote—number/1870, no date.
UNKNOWN; “Demystifying Sigma-Delta ADCs”; Dallas Semiconductor Maxim; http://www.maim-ic.com/appnotes.cfm/appnote—number/1870, Jan. 31, 2003.

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