Digital demodulator for phase shift keyed signals

Details Digital demodulator for phase shift keyed signals Digital demodulator for phase shift keyed signals

1978-08-17

1980-02-26

Bookbinder, Marc E.

Telegraphy

Systems

Printing

178 88, 329104, 329126, H04L 2722

Patent

active

041908023

ABSTRACT:
A digital demodulator for differential phase shift keyed (DPSK) signals includes two pairs of 1-bit integrators for continuously taking the phase difference between successive DPSK bits. Each DPSK bit is subdivided into a plurality of bits, for example 15 bits. A weighted output signal having 4 bits is provided by each 1-bit integrator for each of the bits corresponding to a DPSK bit. The weighted output signals from each pair of 1-bit integrators are sine weighted and multiplied. The products are then added together for application to a comparator. The comparator compares the sum of the addition to a predetermined reference signal and provides a demodulated digital signal having a logical state dependent on whether the sum is greater or smaller than the predetermined reference signal.

REFERENCES:
patent: 3368036 (1968-02-01), Carter et al.
patent: 3493884 (1970-02-01), Kulp
patent: 3568066 (1971-03-01), Fujimura
patent: 3993956 (1976-11-01), Gilmore et al.

Affiliated with

Also associated with

Rating

Digital demodulator for phase shift keyed signals does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Digital demodulator for phase shift keyed signals, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital demodulator for phase shift keyed signals will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2114724