Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2011-03-22
2011-03-22
Ho, Hoai V (Department: 2827)
Static information storage and retrieval
Addressing
Sync/clocking
C365S194000, C365S233100
Reexamination Certificate
active
07911873
ABSTRACT:
An efficient implementation of a digital delay locked loop (DLL) circuit is disclosed. The delay locked loop (DLL) circuit includes a phase detector circuit, a clock divider circuit, a delay, a delay control finite state machine (FSM) and an output low pass filter. The delay includes a coarse delay line and a fine delay line. The coarse delay line delays a signal by a fixed large amount and the fine delay line introduces a smaller precise delay. The delay control FSM adjusts the delay to keep the output signal of the DLL synchronized with the input. The adjustment is averaged over a range of cycle periods in order to avoid adjusting the edges of signal waveform constantly. The low pass filter at the output minimizes the jitter in the output signal.
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Mahajan Raj
Menon Raghavan
Evergreen Valley Law Group P.C.
Ho Hoai V
Radhakrishnan Kanika
Synopsys Inc.
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