Digital delay-locked loop

Details Digital delay-locked loop Digital delay-locked loop

1998-12-10

2000-11-21

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327149, H03L 708

Patent

active

061508594

ABSTRACT:
The present invention is directed to a digital delay-locked loop for digitally controlling a clock signal delay time and saving synchronization information in a register. After intercepting an input clock signal, the digital delay-locked loop utilizes the saved synchronization information in returning to the normal operation, and furthermore, detects a shifted delay by using a trigger pulse generator in order to reduce power consumption during the rapid synchronization of an internal clock signal to an external clock signal, saves a delay state corresponding to a maximum value of half the period of the external clock signal to a lock target rising edge of the internal clock signal, and thus synchronization time and operating time of the digital delay-loop are reduced, which results in reduced operation power for the predetermined time. In addition, even when the external clock signal is suspended, a lock point can be rapidly found and thereby mis-operation because internal clock signals in a circuit are not synchronized to the external clock signal can be minimized.

REFERENCES:
patent: 4604582 (1986-08-01), Strenkowski et al.
patent: 5223755 (1993-06-01), Richley
patent: 5539344 (1996-07-01), Hatakenaka
patent: 5909130 (1999-06-01), Martin et al.

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