Digital delay lock loop

Details Digital delay lock loop Digital delay lock loop

2007-10-16

2007-10-16

Tra, Quan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S158000

Reexamination Certificate

active

11319756

ABSTRACT:
A digital delay locked loop architecture is independent of feedback delay (clock tree delay). The architecture employs a frequency detector circuit which monitors the frequency of the input clock and then sets a division factor for a reference clock used to control delay tap selection. In this way, the architecture can support a fast locking time, coarse tuning and fine-tuning.

REFERENCES:
patent: 2001/0005337 (2001-06-01), Jung
patent: 2005/0024107 (2005-02-01), Takai et al.
patent: 2006/0087353 (2006-04-01), Minzoni et al.

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