Digital delay lines

Details Digital delay lines Digital delay lines

2011-04-26

2011-04-26

Nguyen, Hai L (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S270000

Reexamination Certificate

active

07932765

ABSTRACT:
Some embodiments provide real-time variable delays in a delay line. In some of these embodiments, the real-time variable delays may be enable without producing clock glitches. In an embodiment, delay cells in a delay line may be coupled together in a chain to form a lattice of inverters providing different paths of signal propagation. Each path may have a different number of inverters; each inverter adding a known processing time associated with the signal inversion process. In some embodiments, an input signal may be propagated in an inverted or non-inverted form to the inputs of multiple inverters in the lattice, including the inputs of inverters through which the input signal does not propagate. A desired delay time may be obtained in an embodiment by selecting a path containing a desired number and configuration of inverters. The path may be selected in an embodiment using switchably enabled inverters.

REFERENCES:
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patent: 7119596 (2006-10-01), Kong et al.
patent: 7205803 (2007-04-01), Chung et al.
patent: 2005/0285653 (2005-12-01), Chung et al.
patent: 2006/0267648 (2006-11-01), Kwak
patent: 2008/0068060 (2008-03-01), Hui et al.
PCT International Search Report and Written Opinion mailed on Jul. 28, 2010, for PCT/US2010/37208.

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