Digital delay line with synchronous control

Details Digital delay line with synchronous control Digital delay line with synchronous control

2000-01-18

2004-08-10

Tra, Quan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S158000

Reexamination Certificate

active

06774693

ABSTRACT:

FIELD
The present invention relates to a digital delay line structure with a synchronous single clock domain control.
BACKGROUND
In order to illustrate why a digital delay line is required in a device, an example of the traditional clocking methods is provided.
FIG. 1
shows a simplified schematic of a device using clock tree synthesis. Data is input on pin
11
while clock signals are input on pin
13
. The input signal is applied to pad
10
while the clock input is applied to pad
12
. The set-up and hold delay is represented by circuit elements
14
which are applied to the D input of the flip-flop
18
. The clock tree
16
has an output which is applied to the other input of the flip-flop
18
. For devices using super-clock buffers, the clock tree may be replaced with the super clock buffers. Test logic such as boundary scan has not been considered in this analysis, but may be lumped into the modeled delays.
The lumped delays in
FIG. 1
are analyzed to show the effect of the clock tree. As shown by the timing diagram of
FIG. 2
, the output propagation delay is determined by the input pad delay, the clock tree delay, the flop propagation delay and the output pad delay. For large designs where the clock tree delay is over 4 or 5 ns, the clock tree will dominate the output propagation delay. While custom clock trees, such as using a separate clock tree to the output flip-flop/flops, may help the problem, the tree may still be big enough to significantly affect the output propagation delay.
Since the clock tree delays the clock to the flip-flop sampling the input data, the input data must also be delayed in order to achieve reasonable input setup and hold performance. The delay may be test or functional logic or may be delay chains formed using a string of buffers. In some cases, the propagation difference between a clock input pad and a data input pad requires the input data setup and hold specifications to vary significantly over process voltage and temperature as precise matching of the delays is impossible.
As devices increase in complexity, the clock tree increases in size and latency. While the input setup and hold specifications can be adjusted by increasing the delay on the data inputs, the output propagation delay increases. For extremely large devices with thousands of flip-flops, the clock tree delay may prevent reasonable output propagation delays for high-speed interfaces (for example, the SUNI-622 device manufactured by PMC-Sierra, Inc. of Burnaby, B.C., Canada has an interface with an output propagation close to the clock period). One solution is to use a custom clock tree with high-speed output flip-flops operating on a separate small clock tree. While this solution has been used (for example, in the SUNI-QJET also manufactured by PMC-Sierra, Inc.), devices with a large number of high-speed output flip-flops will still have problems with clock tree latency.
One solution is to use a digital delay locked loop (DLL)
24
as seen in FIG.
3
. In this case the DLL
24
has a SYSCLK input coupled to an output of the clock input pad
12
and a REFCLK (reference clock) input taken from an output of clock tree
26
which is also applied to the input to flip-flop
18
. The DLL generates an internal clock DLLCLK based on the incoming SYSCLK clock input. Since the REFCLK input is connected to the output of the clock tree, the DLLCLK clock output is adjusted until the SYSCLK input and the REFCLK input align. As shown in the timing diagram in
FIG. 4
a rising edge from the clock tree
26
coincides with the rising edge of SYSCLK from the clock input pad
12
. The output propagation specification is now comprised of the clock input pad delay, the flop delay, the output pad delay and the DLL clock uncertainty.
A digital delay locked loop architecture is shown in FIG.
5
. In this case the SYSCLK input is coupled to an adjustable delay line
34
and to a phase detector
30
. Phase detector
30
also has a REFCLK input. The output of the phase detector
30
is directed to a control state machine
32
which directs the amount of delay to be implemented by adjustable delay line
34
in response to the phase difference between SYSCLK and REFCLK. Since the output clock DLLCLK is the same frequency as the system clock SYSCLK, the DLLCLK may be a phase delayed version of the SYSCLK input. A variable delay line controlled by the phase detector produces the required delay to generate the DLLCLK. The control state machine performs many tasks such as filtering the phase detector information and producing status/error control signals for monitoring purposes.
An adjustable delay line has been implemented in many ways. One way is shown in
FIG. 6
in which a chain
33
of buffers
36
,
38
,
40
, etc. forms the delay line with taps taken from the input and at the output of each of the buffers
36
,
38
,
40
, etc. The buffers
36
,
38
,
40
, etc. provide a series of phase delayed copies of the input clock. An output multiplexer
42
selects the desired phase delay from the buffer chain
33
. While the chain
33
of buffers
36
,
38
,
40
, etc. may be easily implemented, the multiplexer
42
is very hard to design as the multiplexer
42
must be able to switch between two clock phases without the output changing at a time that is synchronous with the input clock but with unknown phase delay from the input clock (hereinafter referred to as “glitching”). Most multiplexer implementations use either AND-OR tree logic or pass transistor logic. However, the phase selection must be changed with specific timing in order not to cause a glitch in the output. Usually, local control of the multiplexing function (e.g. a D flip-flop and control logic) is required for each buffer
36
,
38
,
40
, etc. or group of buffers to ensure the output clock does not glitch.
Another common method of implementing a delay line is shown in FIG.
7
. In this case series connected buffers
58
each have a PMOS FET
56
and an NMOS FET
60
in their power supply circuits. The current through PMOS FETs
56
are controlled by a voltage Vcntrl
P
on input
50
and through the NMOS FETs
60
by a related voltage Vcontrl
N
on input line
54
. In this case, the delay of the delay line is adjusted using control currents into the respective buffers
58
. By limiting the current the buffers can draw from the power supply, the delay through the buffer is related to the control current and the capacitance on the buffer's output. While this implementation is very elegant, it requires some analog design for the current mirrors and control voltage generation. While it does not allow for delay jumping, the analog control voltages allow for very precise delay control.
Many other implementations of delay lines exist, but such implementations tend to contain a combination of elements of FIG.
6
and FIG.
7
. For example, an implementation may use the analog delay line in
FIG. 7
, but tune the total delay through the chain to be one clock period. This will produce N equally spaced clock phases, one for each delay stage, which can be selected using the multiplexer in FIG.
6
. Another example may use multiple stages of the delay line in
FIG. 6
to produce a delay line with coarse and fine adjustment control buses.
Most digital approaches seen in publications have a basic structure: the input of the delay line with one clock phase, the output of the delay line with another phase and the control with a third phase. The problem with such an architecture is that three clock domains exist (input, output and control) with the same frequency, but with different phase offsets. In reality, only the input clock domain is important as it controls all logic. All other clock domains are derived (such as the output clock domain) or artificial (such as the control clock domain). There is a need for reduction of the number of clock domains to two.
Accordingly, it is an object of the invention to provide a delay line that is easily controlled using a digital control bus updated at a constant and known phase offset, preferably zero, to the

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