Digital delay line for a reduced jitter digital delay lock loop

Details Digital delay line for a reduced jitter digital delay lock loop Digital delay line for a reduced jitter digital delay lock loop

1996-04-29

1998-07-07

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

327287, 327269, H03K 515

Patent

active

057775010

ABSTRACT:
A delay line having variable delay comprising apparatus for receiving an input clock signal and for providing an inverted and non-inverted version thereof, a plurality of serially connected inverter stages each for receiving and translating the inverted and non-inverted versions of the input clock signal, inverted and non-inverted outputs of each of the inverter stages except a last inverter stage in series being cross-connected to inputs of an immediately following inverter stage, and apparatus for shunting outputs of one of the inverter stages to a pair of output nodes.

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