Digital delay interpolator circuit

Coded data generation or conversion – Analog to or from digital conversion – With particular solid state devices

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H03M 166

Patent

active

057481253

ABSTRACT:
Disclosed is a delay interpolator (DI) circuit (or mixer) that can be driven by digital signals. This DI circuit may be incorporated in the loop of a delay interpolator voltage controlled oscillator (DIVCO) circuit. In turn, the digital DIVCO circuit may be inserted in the loop of a phase-locked loop (PLL) circuit for total digitalization thereof. The novel digital delay interpolator circuit (23) has the base structure of the conventional analog delay interpolator circuit except in that, at the first (bottom) level, the two standard NFET input devices which are normally controlled by an analog signal (typically generated by a preceding DAC) are respectively replaced by two arrays (24A, 24B) of smaller NFET devices connected in parallel. The gate of each NFET device of the first array is driven by a bit (c0, c1, . . . ) of the true phase of the digital signal. The gate of each NFET device of the second array is driven by a bit (c0, c1, . . . ) of the complementary phase of the digital signal. For instance, in the loop of a PLL circuit, this digital signal (Sfilt) is generated by the phase detector, then filtered in a digital filter and stored in a thermometer register. As a result, the DAC is no longer necessary thereby saving significant room and energy consumption.

REFERENCES:
patent: 5428626 (1995-06-01), Frisch et al.
patent: 5489864 (1996-02-01), Ashuri
"Single-Chip 1062MBAUD CMOS Transceiver for Serial Data Communication", pp. 32/33, IEEE International Solid State Circuits Converence, 1 Feb. 1995, 336 XP000566796.

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