Digital delay circuit and digital PLL circuit with first and sec

Details Digital delay circuit and digital PLL circuit with first and sec Digital delay circuit and digital PLL circuit with first and sec

1997-12-04

1999-10-19

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327158, 375376, 331 25, 331DIG2, H03L 706

Patent

active

059695536

ABSTRACT:
A digital delay circuit and a digital PLL circuit achieve reduction in size and power consumption. Each of a first delay line (301) and a second delay line (302) includes a plurality of delay elements. A control circuit (200) selects the delay element(s) included in a delay line (300), and a second clock signal (S11) passes only through the selected delay element(s). That is, the second clock signal (S11) does not pass through the non-selected delay element(s), which reduces power consumption.

REFERENCES:
patent: 5604775 (1997-02-01), Saitoh et al.

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