Digital decode logic for converting successive binary zero pulse

Details Digital decode logic for converting successive binary zero pulse Digital decode logic for converting successive binary zero pulse

1984-01-10

1987-03-17

Safourek, Benedict V.

Pulse or digital communications

Repeaters

Testing

328120, H03K 900

Patent

active

046513299

ABSTRACT:
An apparatus for decoding data wherein only binary ZEROs are received as electronic pulses, each pulse alternating in opposite directions and wherein binary ONEs require no pulse.
The apparatus includes logic for receiving the negative and positive binary ZERO pulses, retiming the pulses and generating a positive pulse for each binary ZERO pulse. The positive pulse is retimed to a pair of complementary pulses and applied to a receiving device, typically a universal synchronous/asynchronous receiver transmitter (USART).

REFERENCES:
patent: 2700696 (1955-01-01), Barker
patent: 3434059 (1969-03-01), Kesolits
patent: 3571736 (1971-03-01), West
patent: 4007382 (1977-02-01), Warberg
patent: 4012785 (1977-03-01), MacDougall, Jr.
patent: 4124888 (1978-11-01), Washburn
patent: 4186375 (1980-01-01), Castellani et al.
patent: 4245215 (1981-01-01), O'Connor et al.
patent: 4277699 (1981-07-01), Brown et al.
patent: 4311962 (1982-01-01), Titsworth
patent: 4374361 (1983-02-01), Holden
patent: 4379993 (1983-04-01), Holden
Motorola-M6800 Microprocessor Application Manual, Motorola, Inc, 1975.

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