Digital data transmission via multi-valued logic signals...

Details Digital data transmission via multi-valued logic signals... Digital data transmission via multi-valued logic signals...

1999-06-03

2002-11-05

Chin, Stephen (Department: 2734)

Pulse or digital communications

Systems using alternating or pulsating current

C326S060000

Reexamination Certificate

active

06477205

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to digital communication systems, and more particularly to unidirectional source-synchronous digital data transmission systems.
2. Description of the Relevant Art
Digital electronic devices typically communicate via electrical signals (e.g., voltages and/or currents) driven upon electrical conductors (e.g., metal wires). Operations within a digital electronic device transmitting data (i.e., a “sender”) may be performed in response to (i.e., synchronized) by a first clock signal, and operations within another digital electronic device receiving the data (i.e., a “receiver”) may be synchronized by a second clock signal. In order for the receiver to receive the data correctly and efficiently, the first and second clocks may need to be synchronized such data reception by the receiver occurs in unison with data transmission by the sender.
FIG. 1
is a diagram of a digital communication system
10
employing source-synchronous data transmission. A sender
12
is coupled to a receiver
14
via n data transmission lines
16
and a clock transmission line
18
. Sender
12
includes n drivers
20
for driving one end of the n data transmission lines
16
according to binary data signals DATA
1
through DATAn, and a driver
22
for driving one end of clock transmission line
18
according to a binary clock signal CLOCK. Sender
12
drives one of two voltage levels upon each of the n data transmission lines
16
dependent upon the logic value of the corresponding binary data signal. Similarly, sender
12
drives one of two voltage levels upon clock transmission line
18
dependent upon the logic value of clock signal CLOCK. Further, sender
12
drives data transmission lines
16
in synchronization with clock signal CLOCK (e.g., in response to a rising or falling transition or “edge” of CLOCK).
Receiver
14
includes n comparators
24
coupled to receive the voltage levels driven upon the n data transmission lines
16
by sender
12
, and a comparator
26
coupled to receive the voltage levels driven upon clock transmission line
18
by sender
12
. Each of the n comparators
24
and comparator
26
also receive a reference voltage level V
REF
, where reference voltage level V
REF
is selected to be between the two voltage levels. Comparator
26
produces binary clock signal CLOCK at an output terminal. Receiver
14
also includes n flip-flops
28
receiving the outputs of the n comparators
24
at input terminals and clock signal CLOCK signal at control terminals. As a result, the n flip-flops
28
produce corresponding data signals DATA
1
through DATAn in response to the CLOCK signal produced by comparator
26
.
As the operating frequencies (i.e., “speeds”) of digital electronic devices increase, electrical conductors used to route signals between components (i.e., signal lines) begin to behave like transmission lines. Transmission lines have characteristic impedances. If the input impedance of a receiving device connected to a transmission line does not match the characteristic impedance of the transmission line, a portion of an incoming signal is reflected back toward a sending device. Such reflections cause the received signal to be distorted. If the distortion is great enough, the receiving device may erroneously interpret the logical value of the incoming signal.
Binary digital signals typically have a low voltage level associated with a logic low (i.e., a logic “0”), a high voltage level associated with a logic high (i.e., a logic “1”), “rise times” associated with transitions from the low voltage level to the high voltage level, and “fall times” associated with transitions from the high voltage level to the low voltage level. A signal line behaves like a transmission line when the signal rise time (or signal fall time) is short with respect to the amount of time required for the signal to travel the length of the signal line (i.e., the propagation delay time of the signal line). As a general rule, a signal line begins to behave like a transmission line when the propagation delay time of the signal line is greater than about one-quarter of the signal rise time (or signal fall time).
Resistive “termination” techniques are often applied to transmission lines, and signal lines long enough to behave like transmission lines, in order to reduce reflections and the resultant signal distortion. One or more electrically resistive elements (e.g., resistors) may be inserted between a driver and an end of a transmission line in order to cause the effective output impedance of the driver to more closely match the characteristic impedance of the transmission line. Similarly, one or more electrically resistive elements may be coupled to an end of a transmission line at a receiver in order to cause the effective input impedance of the receiver to more closely match the characteristic impedance of the transmission line.
FIG. 2
is a diagram of a representative transmission line
30
coupled between sender
12
and receiver
14
, wherein resistive terminations are employed in order to reduce signal reflections and distortion within transmission line
30
. Transmission line
30
may be one of the n data transmission lines
16
or clock transmission line
18
. Switching circuitry
32
within a driver of sender
12
switches a first end of transmission line
30
between a first power supply voltage level V
DD
and a second power supply voltage level V
SS
dependent upon a binary input signal (i.e., a binary data signal or binary clock signal CLOCK). It is noted that second power supply voltage level V
SS
may be a reference ground electrical potential, and V
DD
may be referenced to V
SS
. A first termination resistor
34
, having a value equal to the characteristic impedance Z
O
of transmission line
30
, is connected between switching circuitry
32
and the first end of transmission line
30
in order to reduce signal reflections and distortion within transmission line
30
.
A second end of transmission line
30
is connected a first input terminal of a comparator
36
within receiver
14
. A second termination resistor
38
, having a value equal to the characteristic impedance Z
O
of transmission line
30
, is connected between the first input terminal of comparator
36
and power supply voltage level V
DD
in order to reduce signal reflections and distortion within transmission line
30
.
When first termination resistor
34
and second termination resistor
38
are coupled to opposite ends of transmission line
30
in order to reduce signal reflections and distortion, they form a voltage divider network which restricts the range of voltage levels which may be used to convey binary signals from sender
12
to receiver
14
.
FIG. 3
is a graph of voltage levels V present within sender
12
and upon transmission
30
of FIG.
2
. When switching circuitry
32
connects the first end of transmission line
30
to V
DD
through first termination resistor
34
, a voltage level equal to V
DD
exists at the first end transmission line
30
. When switching circuitry
32
connects the first end of transmission line
30
to V
SS
through first termination resistor
34
, first termination resistor
34
and second termination resistor
38
are connected in series between V
DD
and V
SS
, and a voltage level equal to (V
DD
/2) exists at the first end transmission line
30
(where V
DD
is referenced to V
SS
). As a result, the two voltage levels used to convey binary signals from sender
12
to receiver
14
, V
DD
and (V
DD
/2), exist only in an upper half of the voltage range between V
DD
and V
SS
as shown in FIG.
3
. It is noted that a lower half of the voltage range between V
DD
and V
SS
is unused due to the use of both first termination resistor
34
and second termination resistor
38
.
Reference voltage level V
REF
, connected to a second input terminal of comparator
36
within receiver
14
, is selected between the two voltage levels V
DD
and (V
DD
/2) as described above. Voltage values between (V
DD
/2) and V
REF
re

Affiliated with

Also associated with

Rating

Digital data transmission via multi-valued logic signals... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Digital data transmission via multi-valued logic signals..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital data transmission via multi-valued logic signals... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2991462