Pulse or digital communications – Synchronizers – Frequency or phase control using synchronizing signal
Reexamination Certificate
1998-03-02
2002-05-28
Chin, Stephen (Department: 2734)
Pulse or digital communications
Synchronizers
Frequency or phase control using synchronizing signal
C375S365000, C375S376000, C370S514000
Reexamination Certificate
active
06396888
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a digital data transmission system and, more particularly, to a method of transmitting a frame pulse signal in parallel with data principally within a device in a communication system using frames, packets, and the like.
2. Description of the Background Art
For frame synchronization, conventional frame synchronization type digital data communication systems have employed two methods: a first method wherein a transmitter transmits data in which a frame pattern is embedded and a receiver detects a frame pulse signal from the data, and a second method wherein a transmitter transmits a frame pulse signal in parallel with data.
In general, the first method is employed for data transmission between devices, and the second method is employed for data transmission within a device. In some cases, for bit synchronization with data to be received, the receiver comprises a clock recovery circuit and the transmitter also transmits a clock in parallel with data.
FIG. 31
is a block diagram showing the transmission of a frame pulse signal and a clock in parallel with digital data. As shown, a transmitting portion
39
transmits data DA, a frame pulse signal FP, and a clock CK from drivers
33
to
35
provided therein through transmission lines
51
to
53
respectively to a receiving portion
49
. In
FIG. 31
, the reference numerals
31
and
32
designate flip-flops for processing the data DA and the frame pulse signal FP. The transmission lines
51
to
53
are formed by wires, cables, printed wiring, and the like.
The receiving portion
49
comprises drivers
43
to
45
for receiving the data DA, the frame pulse signal FP, and the clock CK through the transmission lines
51
to
53
, and flip-flops
41
and
42
operating in synchronism with the clock CK for performing signal processing based on the data DA and the frame pulse signal FP. Examples of the clock CK, the frame pulse signal FP and the data DA are shown in FIG.
32
.
The receiving portion
49
is provided for each board corresponding to one or more transmitting LSI circuits of a transmitter.
The digital data transmission system which contains a plurality of lines like a switching system in the above described manner to transmit the data, the frame pulse signal, and the clock in parallel in opposite directions for each line is disadvantageous in that the number of input/output pins of an interface LSI circuit or the number of input/output connectors of a board limit the number of lines to be contained in the digital data transmission system.
FIG. 33
illustrates the connection between N interface LSI circuits
61
to
6
N (where N is a natural number) and a single N×N switch LSI circuit
60
. As shown, since each of the interface LSI circuits
61
to
6
N has six pins for transmitting and receiving the data DA, the frame pulse signal FP, and the clock CK, the switch LSI circuit
60
needs 6·N input/output pins. The interface LSI circuits
61
to
6
N comprise 3-bit output buffer groups G
21
to G
2
N, and 3-bit input buffer groups G
31
to G
3
N, respectively. The switch LSI circuit
60
comprises
3
bit output buffer groups G
41
to G
4
N, and 3-bit input buffer groups G
51
to G
5
N.
M-bit parallel transmission/reception of the data DA requires 2(2+M) input/output pins in each of the interface LSI circuits and accordingly requires 2(2+M)·N pins in the switch LSI circuit
60
. Since the switch LSI circuit
60
requires additional pins for a control signal, the number of lines to be contained in the digital data transmission system (the number of connectable interface LSI circuits) is limited due to the shortage of pins.
The conventional digital data transmission system constructed as above described has required a great number of signal lines when the system must transmit the digital data, the frame pulse signal, and the clock.
Additionally, the frame pulse signal has been multiplexed with the digital data heretofore. However, because of the irregularity of the digital data, much time and high costs are required for the multiplexing of signals in a transmitter and the separation of the signals in a receiver.
SUMMARY OF THE INVENTION
A first aspect of the present invention is intended for a digital data transmission system for transmitting digital data in a frame synchronization manner. According to the present invention, the digital data transmission system comprises a transmitting portion for transmitting digital data, and a receiving portion for receiving the digital data, the transmitting portion comprising a clock multiplexing circuit for multiplexing a frame pulse signal for frame synchronization with a clock having a predetermined period to output a multiple clock to the receiving portion, the receiving portion comprising a clock recovery circuit for reproducing the clock from the multiple clock to provide a recovered clock by using a synchronization loop circuit for synchronizing a reference signal associated with the multiple clock and a comparison output signal, and a frame pulse signal separation circuit for separating the frame pulse signal from the multiple clock to provide a recovered frame pulse signal by using the recovered clock.
Preferably, according to a second aspect of the present invention, in the digital data transmission system of the first aspect, the clock multiplexing circuit includes clock shaping means receiving the clock and the frame pulse signal, the clock shaping means for performing a shaping process of masking the clock at a fixed value at least for the predetermined period during the time the frame pulse signal is active, the clock shaping means for outputting the clock intactly as the multiple clock for other time periods.
Preferably, according to a third aspect of the present invention, in the digital data transmission system of the second aspect, the clock shaping means further receives an enable signal and includes enabling means for disabling the shaping process to force the clock to be outputted intactly as the multiple clock when the enable signal is inactive.
Preferably, according to a fourth aspect of the present invention, in the digital data transmission system of the second aspect, the clock recovery circuit includes: phase comparing means for making a comparison between the phase of the multiple clock and the phase of the recovered clock, control signal output means for outputting a control signal on the basis of a result of the phase comparison of the phase comparing means, and oscillating means for generating the recovered clock at an oscillation frequency based on the control signal, the phase comparing means, the control signal output means, and the oscillating means constituting a PLL circuit for performing a phase synchronization process on the multiple clock and the recovered clock, the synchronization loop circuit including the PLL circuit, the reference signal including the multiple clock, the comparison output signal including the recovered clock.
Preferably, according to a fifth aspect of the present invention, in the digital data transmission system of the fourth aspect, the clock recovery circuit further includes masking means receiving the recovered frame pulse signal, the masking means for disabling the phase synchronization when the recovered frame pulse signal indicates an active state.
Preferably, according to a sixth aspect of the present invention, in the digital data transmission system of the fourth aspect, the clock recovery circuit further includes synchronization detecting means for detecting whether or not the multiple clock and the recovered clock is in synchronism with each other to disable the phase synchronization process upon detection of synchronization.
Preferably, according to a seventh aspect of the present invention, in the digital data transmission system of the second aspect, the clock recovery circuit includes: phase comparing means for making a comparison between the phase of the multiple clock and the phase of a delayed multiple clock,
Ishiwaki Masahiko
Kondoh Harufusa
Notani Hiromi
Yoshimura Tsutomu
Burns Doane , Swecker, Mathis LLP
Chin Stephen
Ha Dac V.
Mitsubishi Denki & Kabushiki Kaisha
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