Digital data transfer synchronization circuit and method

Details Digital data transfer synchronization circuit and method Digital data transfer synchronization circuit and method

1989-06-26

1990-08-14

Safourek, Benedict V.

Pulse or digital communications

Spread spectrum

Direct sequence

307271, H04L 702

Patent

active

049493612

ABSTRACT:
A data transfer synchronization method and circuit allows data to be transferred between two synchronous systems running asynchronously with each other in a way that does not require the receiving system clock to be running twice as fast as the source system clock. Data is clocked into a first set of flip-flops by the clock signal of the source system. The source system clock signal is also used to toggle a toggle flip-flop. The receiving system clock signal is used to clock a first clock bit flip-flop coupled to detect the state of the toggle flip-flop. A delayed version of the receiving system clock signal is used to clock the output of the first set of flip-flops into a second set of flip-flops. The normal (undelayed) receiving system clock signal is used to clock the output of the second set of flip-flops into a third set of flip-flops. A data valid signal is generated when the third set of flip-flops have on their outputs the data received during receiving system clock cycles in which the toggle flip-flop toggled. If the toggle flip-flop did not toggle during a particular receiving system clock cycle, no data valid signal is produced because this data is either redundant or uncertain due to insufficient guaranteed setup time.

REFERENCES:
patent: 4054747 (1977-10-01), Pachynski, Jr.
patent: 4181975 (1980-01-01), Jenkins
patent: 4270183 (1981-05-01), Robinson et al.
patent: 4761635 (1988-08-01), Arnaune et al.
patent: 4805198 (1989-02-01), Stern et al.
patent: 4843617 (1989-06-01), Marshall et al.

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